Usb Interrupt Status Register - Usbisr - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
USB Interrupt Status Register – USBISR
This register specifies the USB interrupt status.
Offset: 0x008
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
EP7IF
Type/Reset WC 0 WC
7
Reserved
Type/Reset
Bits Field
[15:8] EPnIF
[5] ESOFIF
[4] SUSPIF
[3] RSMIF
Rev. 1.30
30 29 28
22 21 20
14 13 12
EP6IF EP5IF EP4IF
0 WC 0 WC
6 5 4
ESOFIF SUSPIF
RW 0 WC
Descriptions
Endpoint n Interrupt Flag (n = 0 ~ 7)
This bit is set by the hardware to indicate the generation of relevant endpoint
interrupt.
Writing 1 into this bit to clear it. It is important to note that the interrupt flag can only
be cleared when the endpoint interrupt status bit in the USBEPnISR register is equal
to 0.
Expected Start Of Frame Interrupt Flag
This bit is set by the hardware when an SOF packet is expected to be received.
The USB host sends an SOF (Start Of Frame) packet each millisecond. If the USB
device hardware does not receive it properly, an ESOF interrupt will be generated
when the ESOFIE bit in the USBIER register is set to 1. If three consecutive ESOF
interrupts are generated, which means that the SOF packet has been missed 3
times, the SUSPIF will be set to 1. This bit will be set to 1 when the missing SOF
packets occur if the timer is not yet locked.
This bit can be read or written. However, only 0 can be written into this bit. Writing 1
has no effect.
Suspend Interrupt Flag
This bit is set by the hardware when no data transfer has occurred for 3ms,
indicating that a suspend request has been sent from the USB host. The suspend
condition check is enabled immediately after a USB reset.
This bit is cleared to 0 by writing 1.
Resume Interrupt Flag
This bit is set by the hardware. When this bit is set to 1, this means that a device
resume has occurred.
This bit is cleared to 0 by writing 1.
571 of 656
27 26
Reserved
19 18
Reserved
11 10
EP3IF EP2IF
0 WC 0 WC 0 WC
3 2
RSMIF URSTIF
0 WC 0 WC 0 WC
25 24
17 16
9 8
EP1IF EP0IF
0 WC 0
1 0
SOFIF Reserved
0
September 28, 2018