Section 2 Data Operations; Using The Dual Data Paths - Motorola DSP56600 Manual

Section 2
DATA OPERATIONS
2.1

USING THE DUAL DATA PATHS

The DSP56300/DSP56600 core can execute a new instruction every
clock cycle. This performance can be used efficiently only if data can
be fed to the core and its results moved out of it at a sufficient rate.
The DSP56300/DSP56600 core's highly parallel architecture was
designed to allow performing the following operations in parallel:
• Data ALU instruction execution
• Up to two parallel moves of data operands or results to/from
the Data ALU
• Up to two address calculations for the next instruction
• Fetch of next instruction
The two data paths (the X bus and Y bus) connect two data memory
sections (the X memory and the Y memory) with the Data ALU.
This parallelism allows the DSP56300/DSP56600 core to execute
more effectively, for example, executing a FIR tap in one clock cycle:
Opcode + operands
____________________________________________
mac x0,y0,a
Data that is moved in parallel into a register is ready for use in the
next instruction, and does not interfere with the current value of the
operands in execution. In the above example, the values of X0 and
Y0 are updated only after the "MAC" instruction uses its operands.
Similarly, data moved from a register will hold the data before it was
updated as a result of execution. For example:
The value of the accumulator A that is moved to the memory is the
value before its update by the "MAC" instruction.
MOTOROLA Optimizing DSP56300/DSP56600 Applications
Data for next
iteration via the X
data bus +
increment pointer
___________________________________
x:(r0)+,x0
mac x0,y0,a
Data for next
iteration via the Y
data bus +
increment pointer
____________________________________
y:(r4)+,y0
a,x:(r0)+
This section
discusses
important features
and new additions
to the DSP56000
core Data
Arithmetic Unit
2-1