Scratch Eeprom; Processor Information Rom And Scratch Eeprom Supported Smbus Transactions - Intel Itanium 2 Processor Datasheet

Table 6-4. Processor Information ROM Format (Sheet 4 of 4)
Offset/
Section
73h
77h
78h
79h
Other
7Ah
NOTES:
1. Refer to the Intel
2. The translation is using BCD.
6.3

Scratch EEPROM

Also available on the SMBus interface on the processor is an EEPROM which may be used for
other data at the system vendor's discretion (Intel will not be using the scratch EEPROM). The data
in this EEPROM, once programmed, can be write-protected by asserting the active-high SMWP
signal. This signal has a weak pull-down (10 kΩ) to allow the EEPROM to be programmed in
systems with no implementation of this signal.
6.4 Processor Information ROM and Scratch EEPROM
Supported SMBus Transactions
The processor information ROM and scratch EEPROM responds to three of the SMBus packet
types: current address read, random address read, and sequential read.
Table 6-5
keeps track of the address accessed during the last read or write operation, incremented by one.
Address "roll over" during reads is from the last byte of the last eight byte page to the first byte of
the first page. "Roll over" during writes is from the last byte of the current eight byte page to the
first byte of the same page.
Table 6-6
address desired to be read. Sequential reads may begin with a current address read or a random
address read. After the SMBus host controller receives the data word, it responds with an
acknowledge. This will continue until the SMBus host controller responds with a negative
acknowledge and a stop.
Table 6-7
as the byte write except that the SMBus host controller does not send a stop after the first data byte
and acknowledge. The Scratch EEPROM internally increments its address. The SMBus host
Datasheet
# of
Function
Bits
32 Processor Feature Flags
4 Number of Devices in TAP
Chain
4 Reserved
8 Checksum
16 Reserved
® ®
Itanium Architecture Software Developer's Manual for details on CPUID registers.
shows the format of the current address read SMBus packet. The internal address counter
shows the format of the random read SMBus packet. The write with no data loads the
shows the format of the byte write SMBus packet. The page write operates the same way
System Management Feature Specifications
Notes
All other are reserved:
[4] =Upper temp reference byte
[3] =Thermal calibration offset
byte present
[2] =SCRATCH EEPROM
present
[1] =Core VID present
One 4-bit hex digit
Reserved for future use
1 byte checksum
Reserved for future use
Examples
1 indicates EEPROM
data for specified field
is valid.
0h
Add up by byte and
take 2's complement.
0000h
85