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PLL Suppression Verification Process
When "Verify calculated phase locked loop suppression" is selected, it is
recommended that "Always Show Suppression Graph" also be selected.
Verifying phase locked loop suppression is a function which is very useful in
detecting errors in the phase detector constant or tune constant, the tune
constant linearity, limited VCO tune port bandwidth conditions, and injection
locking conditions. If the DUT is well behaved (injection locking issues do not
exist or have been eliminated) and the reference source is well behaved (well
known tuning characteristics or a system controlled RF signal generator) then
the need to select PLL suppression verification is minimal.
To verify PLL suppression, a stimulus source is required for the FFT analyzer.
This stimulus signal is connected to the CHIRP INPUT port on the rear panel
of the test set. The PC digitizer, when used as the FFT analyzer, provides a
companion D/A output for this purpose. When an Agilent 89410A vector signal
analyzer is the system FFT analyzer, the 89410A's companion source output is
used.
PLL suppression information
The PLL Suppression View graph has been updated to allow measured,
calculated (adjusted), and theoretical information to be examined more
closely. When the "Always Show Suppression Graph" is selected, the following
graph
Figure 273 Default PLL suppression verification graph
Agilent E5505A User's Guide
(Figure
273) is provided.
e5505a_user_select_suppression.ai
rev2 10/21/03
Advanced Software Features
15
347
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