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Advanced Software Features
PLL Suppression Verification Process
PLL Suppression Verification Process
When "Verify calculated phase locked loop suppression" is selected, it is
recommended that "Always Show Suppression Graph" also be selected.
Verifying phase locked loop suppression is a function which is very useful
in detecting errors in the phase detector constant or tune constant, the tune
constant linearity, limited VCO tune port bandwidth conditions, and
injection locking conditions. If the DUT is well behaved (injection locking
issues do not exist or have been eliminated) and the reference source is well
behaved (well known tuning characteristics or a system controlled RF signal
generator) then the need to select PLL suppression verification is minimal.
To verify PLL suppression, a stimulus source is required for the FFT
analyzer. This stimulus signal is connected to the "Noise Input" port on the
rear-panel of the Agilent/HP 70420A test set. For the E550xB systems, the
PC digitizer used as the FFT analyzer also provides a companion D/A output
to be used for this purpose. When an Agilent/HP 89410A vector signal
analyzer is the system FFT analyzer, the Agilent/HP 89410As companion
source output is used. For the E550xA systems, the Agilent/HP
E1441A VXI arbitrary source is used as the stimulus signal for the
Agilent/HP E1430A VXI digitizer and is connected per
Figure
16-2.
NOTE
The sync output from the Agilent/HP E1441A MUST Connect to both the
Ext trigger inputs - use a BNC "T".
Figure 16-2
Using the E1441A as a Stimulus Response for the E1430A
Agilent Technologies E5500 Phase Noise Measurement System 16-7
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