Nortel Circuit Card Installation Manual page 740

Page 740 of 906
Table 238
System clock specification and characteristics
Specifications
Base Frequency
Accuracy
Operating Temperature
Drift Rate (Aging)
Tuning Range (minimum)
Input Voltage Range
553-3001-211 Standard 3.00
NTAK20 Clock Controller daughterboard
System clock specification and characteristics
Since the accuracy requirements for CCITT and EIA Stratum 3 are different,
it is necessary to have two TCVCXOs which feature different values of
frequency tuning sensitivity. See Table 238.
CCITT
20.48 MHz
+ 3 ppm
0 to 70 C + 1 ppm
+ 1 ppm per year
+ 60 ppm min.
+ 90 ppm max.
0 to 10 volts, 5V center
EIA/CCITT compliance
The clock controller complies with 1.5 Mb EIA Stratum 3ND, 2.0 Mb CCITT
or 2.56 Mb basic rate. The differences between these requirements mainly
affect PLL pull in range. Stratum 4 conforms to international markets
(2.0 Mb) while Stratum 3 conforms to North American markets (1.5 Mb).
Monitoring references
The primary and secondary synchronization references are continuously
monitored in order to provide autorecovery.
Reference switchover
Switchover occurs in the case of reference degradation or loss of signal.
When performance of the reference degrades to a point where the system
clock is no longer allowed to follow the timing signal, then the reference is
out of specification. If the reference is out of specification and the other
reference is still within specification, an automatic switchover is initiated
August 2005
EIA
20.48 MHz
+ 1 ppm
0 to 70 C + 1 ppm
+ 4 ppm in 20 years
+ 10 ppm min.
+ 15 ppm max.
0 to 10 volts, 5V center