Figure 83
MSDL block diagram
CPU Bus
MPU Bus
DMA
Arbitrator
Address Buffer and
Decoding Logic
Shared Resource
Arbitrator
MPU Address
Decoding Logic
Micro Processing Unit
(68020 MPU)
Memory
Parallel I/O
Controller
RS-232
RS-232/422
Transceiver
Transceiver
Monitor Port
Port 0
NT6D80 MSDL card
Control and Data
Transceivers
Interface Registers
Memory Address
Counter & Buffer
Integrated Serial Communication Controllers
RS-232/422
RS-232/422
Transceiver
Transceiver
Port 1
Circuit Card
Page 393 of 906
Address Bus
Control Bus
Data Bus
Shared Memory
Address Bus
Control Bus
Data Bus
RS-232/422
Transceiver
Port 2
Port 3
553-5432
Description and Installation