Dma Channel Control Registers (Dmao_Cro-Dmao_Cr3) - IBM PowerPC 405GP User Manual

8:11 RI[0:3] Channel 0-3 Error Status See "Errors" on page 18-14 for more
o
No error
information.
1 Error occurred
12:15 IR[0:3] Internal DMA Request
o
No internal DMA request pending
1 Internal DMA request is pending
16:19 ER[0:3] External DMA Request
o
No external DMA request pending
1 External DMA request is pending
20:23 CB[0:3]
Channel Busy
o
Channel is idle
1 Channel currently active
24:27 SG[0:3] Scatter/Gather Status
o
No scatter/gather operation in progress
1 Scatter/gather operation in progress
28:31 Reserved
18.3.4 DMA Channel Control Registers (DMAO_CRO-DMAO_CR3)
The DMA Channel Control Registers (DMAO_CRO-DMAO_CR3) are used to configure and enable
their respective DMA channels. Before a DMA channel can transfer data, the channel control, source
address, destination address, and transfer count registers must be programmed. If a DMA channel is
setup for scatter/gather transfers (DMA_SGC[SSGn]=1) the DMA channel control register is
automatically loaded from memory. For additional details see "Scatter/Gather Transfers" on
page 18-16.
PWC
+
PHC TCE PF
DEC
Figure 18-5. DMA Channel Control Registers (DMAO_CRO-DMAO_CR3)
0
CE
Channel Enable This field is automatically cleared when
o
Channel is disabled
the transfer completes or an error occurs.
1 Channel is enabled
1 CIE
Channel Interrupt Enable When enabled, interrupts are generated
o
Disable interrupts from this channel for terminal count, end of transfer, and
1 Enable interrupts from this channel
errors conditions. See "DMA Interrupts"
on page 18-15.
18-8 PPC405GP User's Manual Preliminary