Auto (Cas Before Ras) Refresh; Refresh Timer Register (Sdramo_Rtr) - IBM PowerPC 405GP User Manual

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Self Refresh Exit
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Figure 15-to. Self-Refresh Entry and Exit
15.3.8 Auto (CAS Before RAS) Refresh
Refresh of odd memory banks is staggered from the refresh of even memory banks. Only enabled
SDRAM banks (SDRAMO_BnCR[BE]=1) are initialized when the controller is enabled
(SDRAMO_CFG[DCE] set to 1) and refreshed during normal operation. Once the memory controller
is enabled and the initialization sequence has completed, the refresh mechanism starts automatically
with refreshing of the memory continuing independent of SDRAMO_CFG[DCE].
Refresh requests are generated internally when the refresh timer expires. The refresh interval is
program~able
via the Refresh Timer Register (SDRAMO_RTR). During refresh, all SDRAM accesses
are delayed until the refresh cycle completes.
15.3.9 Refresh Timer Register (SDRAMO_RTR)
The Refresh Timer Register determines the memory refresh rate for the SDRAM. The internal
counter runs at the controller clock frequency, thus if MemClkOut1 :0 is 100 MHz, a value of Ox05FO
produces a refresh interval of 15.20 s (1520 x 10 ns = 15.20s). This register is progammable to
accommodate other SDRAM clock frequencies.
SDRAM Controller 15-13