Pmm 1 Mask/Attribute Register (Pcilo_Pmm1Ma); Pmm 1 Pci Low Address Register (Pcilo_Pmm1Pcila) - IBM PowerPC 405GP User Manual

17.5.2.6 PMM 1 Mask/Attribute Register (PCILO_PMM1MA)
PCllO_PMM1 MA defines the size and attributes of range 1 in PlB space that is mapped to PCI
memory. See "PMM
°
Mask/Attribute Register (PCllO_PMMOMA)" on page 17-22.
MASK
t
ENA
+
12111
2j 1
1
0
1
t
PRE
Figure 17-12. PMM 1 Mask/Attribute Register (PCllO_PMM1MA)
31:12 MASK The mask bits determine the size of the The mask must be of the form 111 .... 0000.
address map range. Bits set to 1 cause the corresponding
PCILO_PMM1 LA bits to be compared with
incoming PLB addresses. Note that the
minimum range size is 4KB, and valid
ranges are powers of 2. For example, a
128MB range would be encoded as
OxF8000 and a 4KB range would be
encoded as Ox11111.
11 :2 Reserved Returns 0 when read.
,
1
PRE
Read Prefetching Enable If read prefetch is enabled, the PCI bridge
1 Read prefetching is enabled. prefetches 64 bytes from PCI memory in
response to a PLB single-beat, byte-burst,
or half word burst read from PMM
o.
0 ENA PLB to PCI Memory Mapping Enable Note that PCILO_PMM1 LA,
1 Memory mapping is enabled. PCILO_PMM1 PCIHA, and
PCILO_PMM1 PCILA must be initialized
before enabling.
17.5.2.7 PMM 1 PCI Low Address Register (PCILO_PMM1PCILA)
PCllO_PMM1 PCllA defines the low-order 32 bits of the PCI address generated in response to a PlB
access to range 1. See "PMM
°
PCI low Address Register (PCllO_PMMOPCllA)" on page 17-22.
01
Figure 17-13. PMM 1 PCI low Address Register (PCllO_PMM1 PCllA)
I
31:0
I
PCI Low Address
17-24
PPC405GP User's Manual Preliminary