IBM PowerPC 405GP User Manual page 543

Embedded processor
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3
FC
First Channel
EMACO_ TMRO[FC) is only meaningful in
o
Activate TX Channel 0 first when GNPD
dependent mode, after resetting
is 1
EMACO_ISR[DBDM).
1 Activate TX Channel 1 first when GNPD
EMACO_ TMRO[FC]
=
0 if EMAC is not
is 1
programmed in dependent mode.
4:31
Reserved
19.7.4 Transmit Mode Register 1 (EMACO_TMR1)
EMACO_ TMR1 defines conditions for activation of MAL service requests during transmit operations
(see "EMAC Transmit Operation" on page 19-5).
19.7.4.1 Low-Priority Requests
EMAC requests low priority service from MAL when the number of vacant entries in the TX FIFO
exceeds the decimal TLR value.
EMACO_ TMR1 [TRL] must at least equal ((MAL Burst Limit / 2)-1). For example, if MAL supports 16-
word bursts, the decimal TLR value should be at least 7.
Note: In the 405GP, all MAL channels are capable of 16 word bursts.
To avoid a deadlock, the sum of EMACO_ TMR1 [TRL] and EMACO_ TRTR[TRT] must be at least 4
smaller than the transmit FIFO size specified by EMACO_MR1 [TFS].
19.7.4.2 Urgent-Priority Requests
EMAC requests urgent priority service from MAL if the following conditions occur:
• EMAC begins transmitting the packet to the media before the entire packet is placed in the TX
FIFO
• The number of vacant entries for the currently transmitting packet exceeds the decimal TUR value
Software must coordinate the value of EMACO_ TMR1 [TUR] with the value of EMACO_MR1 [TFS].The
value of EMACO_ TMR1 [TUR] must be smaller than that of EMACO_MR1 [TFS] so that the array
address encoded in EMACO_ TMR1 [TUR] can access the full 66-bit wide array.
The binary value of EMACO_ TMR1 [TUR] must be greater than that ofEMACO_ TMR1 [TLR].
The EMACO_ TMR1 contents can be
cha~ged
only when EMACO_ TMRO[GNPO, GNP1, GNPD]
=
0.
TLR
*
1
0
f
15
1
1 6
31!
TUR
Figure 19-18. Transmit Mode Register 1 (EMACO_ TMR1)
0:4
TLR
Transmit Low Request
5:7
Reserved
8:15
TUR
Transmit Urgent Request
19-28
PPC405GP User's Manual
Preliminary

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