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Figure 25-62. IICO Control Register (IICO_CNTL) ..................................................................................... 25-100
Figure 25-63. IICO Direct Control Register (IICO_DIRECTCNTL) ............................................................. 25-1 01
Figure 25-64. IICO Extended Status Register (IICO_EXTSTS) ................................................................. 25-1 02
Figure 25-65. IICO High Master Address Register (IICO_HMADR) ........................................................... 25-104
Figure 25-66. IICO High Slave Address Register (IICO_HSADR) ............................................................. 25-105
Figure 25-67. IICO Interrupt Mask Register (IICO_INTRMSK) .................................................................. 25-1 06
Figure 25-68. IICO Low Master Address Register (IICO_LMADR) ............................................................ 25-107
Figure 25-69. IICO Low Slave Address Register (IICO_LSADR) ............................................................... 25-108
Figure 25-70. IICO Master Data Buffer (IICO_MDBUF) ............................................................................. 25-109
Figure 25-71. IICO Mode Control Register (IICO_MDCNTL) ..................................................................... 25-110
Figure 25-72. IICO Slave Data Buffer (IICO_SDBUF) ................................................................................. 25-111
Figure 25-73. IICO Status Register (IICO_STS) ...........
~
............................................................................ 25-112
Figure 25-74. IICO Transfer Count Register (IICO_XFRCNT) ................................................................... 25-113
Figure 25-75. IICO Extended Control and Slave Status Register (IICO_XTCNTLSS) ............................... 25-114
Figure 25-76. Link Register (LR) ............................................................................................................... 25-116
Figure 25-77. MAL Configuration Register (MALO_CFG) ......................................................................... 25-117
Figure 25-78. MAL Error Status Register (MALO_ESR) ........................................................................... 25-119
Figure 25-79. MAL Interrupt Enable Register (MALO_IER) ...................................................................... 25-121
Figure 25-80. RX Channel Buffer Size Register
°
(MALO_RCBSO) ........................................................ 25-122
Figure 25-81. RX ChanneLActive Reset Register (MALO_RXCARR) ...................................................... 25-123
Figure 25-82. RX ChanneLActive Set Register (MALO_RXCASR) .......................................................... 25-124
Figure 25-83. RX Channel Table Pointer x Register (MALO_RXCTPxR) ................................................. 25-125
Figure 25-84. RX Descriptor Error Interrupt Register (MALO_RXDEIR) ................................................... 25-126
Figure 25-85. RX End of Buffer Interrupt Status Register (MALO_RXEOBISR) ....................................... 25-127
Figure 25-86. TX Channel_Active Reset Register (MALO_TXCARR) ...................................................... 25-128
Figure 25-87. TX ChanneLActive Set Register (MALO_TXCASR) ........................................................... 25-129
Figure 25-88. TX Channel Table Pointer x Register (MALO_ TXCTPxR) .................................................. 25-130
Figure 25-89. TX Descriptor Error Interrupt Register (MALO_ TXDEIR) .................................................... 25-131
Figure 25-90. TX End of Buffer Interrupt Status Register (MALO_ TXEOBISR) ........................................ 25-132
Figure 25-91. Machine State Register (MSR) ........................................................................................... 25-133
Figure 25-92. OCM Data-Side Address Range Compare Register (OCMO_DSARC) .............................. 25-135
Figure 25-93. OCM Data-Side Control Register (OCMO_DSCNTL) ......................................................... 25-136
Figure 25-94. OCM Instruction-Side Address Range Compare Register (OCMO_ISARC) ...................... 25-137
Figure 25-95. OCM Instruction-Side Control Register (OCMO_ISCNTL) .................................................. 25-138
Figure 25-96. OPB Arbiter Control Register (OPBAO_CR) ....................................................................... 25-139
Figure 25-97. OPB Arbiter Priority Register (OPBAO_PR) ....................... : ............................................... 25-140
Figure 25-98. PCI Base Address Register (PCICO_BARO) ...................................................................... 25-141
Figure 25-99. PCI Built-in Self Test Control Register (PCICO_BIST) ....................................................... 25-142
Figure 25-100. Bridge Options 1 Register (PCICO_BRDGOPT1) ............................................................. 25-143
Figure 25-101. Bridge Options 2 Register (PCICO_BRDGOPT2) ............................................................. 25-144
Figure 25-102. PCI Cache Line Size Register (PCICO_CACHELS) ......................................................... 25-145
Figure 25-103. PCI Capabilities Pointer (PCICO_CAP) ............................................................................ 25-146
Figure 25-104. Capability Identifier (PCICO_CAPID) ................................................................................ 25-147
Figure 25-105. PCI Configuration Address Register (PCICO_CFGADDR) ............................................... 25-148
Figure 25-106. PCI Configuration Data Register (PCICO_CFGDATA) ..................................................... 25-149
Figure 25-107. PCI Class Register (PCICO_PCICLS) .............................................................................. 25-150
Preliminary
Figures
xxxvii
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