IBM PowerPC 405GP User Manual page 147

7 LWOA Load Without Allocate
o
Load misses result in line fills
1 Load misses do not result in a line fill, but
in non-cachable loads
8 SWOA Store Without Allocate
o
Store misses result in line fills
1 Store misses do not result in line fills, but
in non-cachable stores
9 DPP1 DCU PLB Priority Bit 1 Note: DCU logic dynamically controls DCU
o
DCU PLB priority 0 on bit 1 priority bit
o.
1 DCU PLB priority 1 on bit 1
10:11 IPP ICU PLB Priority Bits 0:1
00 Lowest ICU PLB priority
01 Next to lowest ICU PLB priority
10 Next to highest ICU PLB priority
11 Highest ICU PLB priority
12:13
....
Reserved
.........
. . .
"
..
14 UOXE Enable UO Exception
o
Enables the UO exception
1 Disables the UO exception
15 LOBE Load Debug Enable
o
Load data is invisible on data-side (on-
chip memory (OCM)
1 Load data is visible on data-side OCM
16:19
••••
.....
Reserved
.
....
20 PFC ICU Prefetching for Cachable Regions
o
Disables prefetching for cachable
regions
1 Enables prefetching for cachable regions
21 PFNC ICU Prefetching for Non-Cachable Regions
o
Disables prefetching for non-cachable
regions
1 Enables prefetching for non-cachable
regions
22 NCRS Non-cachable ICU request size
o
Requests are for four-word lines
1 Requests are for eight-word lines
23 FWOA Fetch Without Allocate
o
An ICU miss results in a line fill.
1 An ICU miss does not cause a line fill,
but results in a non-cachable fetch.
24:26
lli·.·····j··~(~
Reserved
27 CIS Cache Information Select
o
Information is cache data.
1 Information is cache tag .
28:30
.........•.....••.•.....•.••.....•.•
:
...•...•.•.
Reserved
4-12
PPC405GP User's Manual Preliminary