Table of Contents
Advertisement
\ 0
11
31\
Figure 20-15. RX Channel_Active Reset Register (MALO_RXCARR)
0
Receive Channel Active Reset
Each bit represents its related
channel (bit 0 for channel 0, etc.).
When 0 is written to the bit, channel
operation is disabled.
There is only one RX channel in the
PPC405GP.
1:31
Reserved
20.8.2.1 End of Buffer Interrupt Status Registers
Each bit in the TX End-of-Buffer Interrupt Status and RX End-of-Buffer Interrupt Status registers is
related to a channel's descriptor buffer table.
The TX End-of-Buffer Interrupt Status register contains the End-of-Buffer Status bits for each TX
channel. The RX End-of-Buffer Interrupt Status register contains the End-of-Buffer Status bits for the
RX channels. The mechanism (as described below) for both RX and TX registers is the same.
MAL sets a channel's bit in one of the following conditions:
• When MAL finishes the processing of a buffer (writes back the status to the current descriptor), the
related bit in this register is set if the I bit in the descriptor status is set.
• When MAL finishes the processing of a packet (writes back the status of the packet's last buffer)
and MALO_MGR[EOPIE] is set.
Note:
In case MAL finishes the processing of a packet which is backed up, MAL doesn't consider it
as an end of packet. Therefore, MAL will not set the appropriate channel bit in the End-of-
Buffer Register.
• When the Bad Packet bit is set in the GOMMAG channel Status halfword.
The device driver resets the interrupt by writing a 1 to the related bit. Writing a
°
has no effect.
\0
112
Figure 20-16. TX End of Buffer Interrupt Status Register (MALO_ TXEOBISR)
0:1
Transmit Channel End-ot-Buffer Interrupt
Each bit represents its related
channel (bit 0 tor channel 0, etc.).
Writing 1 to a bit resets it.
There are only two TX channels in the
PPC405GP .
2:31
I
..•••..
.. Reserved
20-28
PPC405GP User's Manual
Preliminary
Advertisement
Chapters
Table of Contents
