(Pcico_Plbbesro); Plb Slave Error Syndrome Register 1 (Pcico_Plbbesr1) - IBM PowerPC 405GP User Manual

Embedded processor
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13:11
M3ET
Master 3 Error Type
See PCICO_PLBBESRO[MOET]
10
M3RWS
Master 3 Read/Write Status
o
Error operation was a write
1 Error operation was a read
9
M3FL
Master 3 PCICO_PLBBESRO Field Lock
o
PCICO_PLBBESRO unlocked
1 PCICO_PLBBESRO locked
8
M3AL
Master 3 PCICO_PLBBEAR Address Lock
o
PCICO_PLBBEAR Unlocked by Master 2
1 PCICO_PLBBEAR Locked by Master 2
7:0
Reserved
17.5.3.28 PLB Slave Error Syndrome Register 1 (PCICO_PLBBESR1)
PCICO_PLBBESR1 stores information about errors reported by the bridge PLB slave. There are four
groups of errors, one each for PLB masters 4-7. See "PLB Slave Error Syndrome Register
°
(PCICO_PLBBESRO)" on page 17-45 for additional information about the fields of this register.
Only software can clear PCICO_PLBBESR1 [MxFL]. The PCICO_PLBBESR1 [MxAL] fields control the
and PCICO_PLBBESRO and PCICO_PLBBESR1 in the same way. Writing a 1 to a field of the
PCICO_PLBBESRx clears the bit.
M4ET
M4FL
M5ET
M5FL
M6ET
M6FL
M7ET
M7FL
7
o
M4RWSM4AL
M5RWS M5AL
M6RWSM6AL
M7RWS M7AL
Figure 17·49. PLB Slave Error Syndrome 1 (PCICO_PLBBESR1)
31:29
M4ET
Master 4 Error Type
000 No Error
001 Parity Error
010 Reserved
011 Reserved
100 Reserved
101 Non-configured Bank Error
110 Reserved
111 Reserved
28
M4RWS
Master 4 Read/Write Status
o
Write error operation
1 Read error operation
27
M4FL
Master 4 PCICO_PLBBESR1 Field Lock
o
PCICO_PLBBE,SR1 unlocked
1 PCICO_PLBBESR1 locked
Preliminary
PCllnterface
17·47

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