IBM PowerPC 405GP User Manual page 604

DLAB SP PEN WLS
... ... ...
...
10111213141516 71
f f f
SB EPS SBS
Figure 21-6. UART Line Control Registers (UARTx_LCR)
0 DLAB Divisor Latch Access Bit
o
Address RBR, THR and IER with
LTADR2-0 for read or write operation
1 Address Divisor Latches with LTADR2-0
for read or write operation
1 SB Set Break
Causes a break condition to be transmitted
o
Disable Break to the UART when the core is receiving.
1 Enable Break
SOUT is forced to the spacing state (0).
This bit acts only on SOUT and has no
effect on the transmitter logic.
2
SP
Sticky Parity If UARTx_LCR[EPS]
=
1 and
o
Disable sticky parity
UARTx_LCR[PE]
=
1, the parity bit is
1 Enable sticky parity
transmitted and checked as O. If
UARTx_LCR [EPS]
=
0 and
UARTx_LCR[PE]
=
1 ,the parity bit is
transmitted and checked as 1.
3 EPS Even Parity Select This bit is significant only if
o
Generate odd parity
UARTx_LCR[PE]
=
1.
1 Generate even parity
4 PEN Parity Enable
o
Disable parity checking
1 Enable parity checking
5 SBS Stop Bit Select If UARTx_LCR[CL]
=
00, characters have
o
Characters have 1 stop bit 1.5 stop bits. For any other value of
1 Characters have 1.5 or 2 stop bits
UARTx_LCR[CL], characters have 2 stop
bits.
The receiver checks the first stop bit only,
regardless of how many stop bits are
selected.
6:7 WLSO, Word Length Select Bits 0,1
WLS1 00 Use 5-bit characters
01 Use 6-bit characters
10 Use 7 -bit characters
11 Use 8-bit characters
Note: UARTx_LCR is shown in standard PowerPC bit notation, where 0 is the MSb and 7 is the LSb.
Preliminary Serial Port Operations
21-9