IBM PowerPC 405GP User Manual page 581

For TX channels, a descriptor error occurs when MAL accesses a descriptor in which the Ready bit
is cleared. The following cases are exceptions.
- On access to the first buffer descriptor in a TX packet.
- <?n access to a buffer descriptor that is not the last descriptor in a backed-up packet.
As a result of this error, the following actions are taken by MAL:
- The Active bit of the related channel is reset and the channel activity is halted until software
reactivates channel activity.
- The associated bit in the TX Descriptor Interrupt Error Register (MALO_ TXDEIR) or RX
Descriptor Error Register (MALO_RXDEIR) is set, causing a nonmaskable TXDE interrupt or
RXDE interrupt respectively.
- When the channel is reactivated, MAL points to the descriptor at the head of the BD table.
• OPB Non-Fullword Error
This error indicates that a non-fullword acknowledge was asserted by a slave.
Following this error, the active bit of the associated channel is reset and channel activity is halted
until it is reactivated by software. When the channel is reactivated, MAL points to the descriptor at
the head of the BD table.
• OPB Time-OutError
This error indicates that an OPB time-out error was reported by the OPB arbiter.
Following this error, the active bit of the associated channel is reset and channel activity is halted
until reactivated by software. When the channel is reactivated, MAL points to the descriptor at the
head of the BD table.
• OPB Error
This error indicates that an OPB error was detected.
Following this error, the active bit of the associated channel is reset and channel activity is halted
until reactivated by software. When the channel is reactivated, MAL points to the descriptor at the
head of the BD table.
• PLB Error
This error indicates that a PLB error was detected (from the PLB slave).
In this case, MAL cannot determine which channel caused the error. Therefore, operation is not
halted for any of the channels.
20.7.3.3 Error Handling Registers
MAL error handling logic includes two registers.
• Error Status Register (ESR)
This register holds information about the error that occurred and the interrupt status. The register
includes the following fields:
Error status - This field holds the error information. The information includes the number of the
channel on which the error occurred (if known) and the type of the error. The error can be either the
last detected error or a locked error if "Locked error mode" is active. See "Operational Error Modes"
on page 20-21 for description of the Locked error mode.
20-20 PPC405GP User's Manual Preliminary