Pci Bridge Local Configuration Registers - IBM PowerPC 405GP User Manual

Table 17-10. PCI Configuration Register Offsets (continued)
Access
Register Offset PLB PCI Description
PCICO_ERREN Ox48 RIW
RIW
Error Enable
PCICO_ERRSTS Ox49 RIW RIW Error Status
PCICO_BRDGOPT1 Ox4B-Ox4A RIW
RIW
PCI Bridge Options 1
PCICO_PLBBESRO Ox4F-Ox4C
RIW RIW PLB Slave Error Syndrome 0
PCICO_PLBBESR 1
Ox53-0x50 RIW RIW PLB Slave Error Syndrome 1
PCICO_PLBBEAR Ox57-0x54 RIW RIW PLB Slave Error Address Register
PCICO_CAPID Ox58 R
R
Capability Identifier
PCICO_NEXTIPTR
Ox59 R R Next Item Pointer
PCICO_PMC Ox5B-Ox5A R R Power Management Capabilities
PCICO_PMCSR Ox5D-Ox5C RIW RIW Power Management Control Status
PCICO_PMCSRBSE Ox5E R
R
PMCSR PCI-to-PCI Bridge Support Extensions
PC I CO_DATA
Ox5F R R Data
PCICO_BRDGOPT2 Ox63-0x60 RIW RIW PCI Bridge Options 2
PCICO_PMSCRR Ox64
RIW RIW Power Management State Change Request
Register
17.5.2 PCI Bridge Local Configuration Registers
The PCI bridge local configuration registers have fixed addresses in PLB space and must be
accessed using single beat PLB read or write cycles of the same size as shown in the register
descriptions.
Failure to access all bytes of a particular register could produce unexpected results. Reading of
reserved bit locations produces unpredictable values. Software must use appropriate masks to
extract the desired bits. Writes must preserve the values of reserved bit positions by first reading the
register, merging the new value, and writing the result.
17.5.2.1 PMM 0 Local Address Register (PCILO_PMMOLA)
PCILO_PMMOLA defines the PLB starting address of range 0 in PLB space that is mapped to PCI
memory. Only bits that are 1 in the PCILO_PMMOMA are used to determine the starting address; all
other bits are don't cares. Only bits 31 :12 are writable. Bits 11:0 are always O.
WLA
+
1
31
12111
01
Figure 17-7. PMM 0 Local Address Register (PCILO_PMMOLA)
31:12 WLA
Writable PLB Local Address
11 :0 PLB Local Address Always 0
Preliminary
PCI Interface 17-21