IBM PowerPC 405GP User Manual page 39

Figure 25-108. PCI Command Register (PCICO_CMD) ........................................................................... 25-151
Figure 25-109. PCI Data (PCICO_DATA) ................................................................................................. 25-153
Figure 25-110. PCI Device ID Register (PCICO_DEVID) ......................................................................... 25-154
Figure 25-111. Error Enable Register (PCICO_ERREN) .......................................................................... 25-155
Figure 25-112. Error Status Register (PCICO_ERRSTS) ......................................................................... 25-156
Figure 25-113. PCI Header Type Register (PCICO_HDTYPE) ................................................................ 25-157
Figure 25-114. PCllnterrupt Control/Status Register ............................................................................... 25-158
Figure 25-115. PCI Interrupt Line Register (PCICO_INTLN) .................................................................... 25-159
Figure 25-116. PCI Interrupt Pin Register (PCICO_INTPN) ..................................................................... 25-160
Figure 25-117. PCI Latency Timer Register (PCICO_LATTIM) ................................................................ 25-161
Figure 25-118. PCI Maximum Latency Register (PCICO_MAXL TNCY) ................................................... 25-162
Figure 25-119. PCI Minimum Grant Register (PCICO_MINGNT) ............................................................. 25-163
Figure 25-120. Next Item Pointer (PCICO_NEXTIPTR) ............................................................................ 25-164
Figure 25-121. PLB Slave Error Address Register (PCICO_PLBBEAR) .................................................. 25-165
Figure 25-122. PLB Slave Error Syndrome Register
°
(PCICO_PLBBESRO) .......................................... 25-166
Figure 25-123. PLB Slave Error Syndrome 1 (PCICO_PLBBESR1) ........................................................ 25-168
Figure 25-124. Power Management Capabilities Register (PCICO_PMC) ............................................... ·25-170
Figure 25-125. Power Management Control/Status Register (PCICO_PMCSR) ...................................... 25-171
Figure 25-126. PMCSR PCI to PCI Bridge Support Extensions (PCICO_PMCSRBSE) .......................... 25-172
Figure 25-127. Power Management State Change Request Register (PCICO_PMSCRR) ...................... 25-173
Figure 25-128. PCI PTM 1 BAR Register (PCICO_PTM1BAR) ................................................................ 25-174
Figure 25-129. PCI PTM 2 BAR Register (PCICO_PTM2BAR) ................................................................ 25-175
Figure 25-130. PCI Revision ID Register (PCICO_REVID) ...................................................................... 25-176
Figure 25-131. PCI Subsystem ID Register (PCICO_SBSYSID) .............................................................. 25-177
Figure 25-132. PCI Subsystem Vendor ID Register (pCICO_SBSYSVID) ............................................... 25-178
Figure 25-133. PCI Status Register (PCICO_STATUS) ........................................................................... 25-179
Figure 25-134. PCI Vendor ID Register (PCICO_VENDID) ...................................................................... 25-181
Figure 25-135. PMM
°
Local Address Register (PCILO_PMMOLA) ......................................................... 25-182
Figure 25-136. PMM
°
Mask/Attribute Register (PCILO_PMMOMA) ........................................................ 25-183
Figure 25-137. PMM 1 PCI High Address Register (PCILO_PMM1 PCIHA) ............................................. 25-184
Figure 25-138. PMM
°
PCI Low Address Register (PCILO_PMMOPCILA) .............................................. 25-185
Figure 25-139. PMM 1 Local Address Register (PCILO_PMM1 LA) ......................................................... 25-186
Figure 25-140. PMM 1 Mask/Attribute Register (PCILO_PMM1 MA) ........................................................ 25-187
Figure 25-141. PMM 1 PCI High Address Register (PCILO_PMM1 PCIHA) ............................................. 25-188
Figure 25-142. PMM 1 PCI Low Address Register (PCILO_PMM1 PCILA) .............................................. 25-189
Figure 25-143. PMM 2 Local Address Register (PCILO_PMM2LA) ......................................................... 25-190
Figure 25-144. PMM 2 Mask/Attribute Register (PCILO_PMM2MA) ........................................................ 25-191
Figure 25-145. PMM 2 PCI High Address Register (PCILO_PMM2PCIHA) ............................................. 25-192
Figure 25-146. PMM 2 Low Address Register (PCILO_PMM2PCILA) ..................................................... 25-193
Figure 25-147. PTM 2 Local Address Register (PCILO_PTM1 LA) ........................................................... 25-194
Figure 25-148. PTM 1 Memory Size/Attribute Register (PCILO_PTM1 MS) .............................................. 25-195
Figure 25-149. PTM 2 Local Address Register (PCILO_PTM2LA) ........................................................... 25-196
Figure 25-150. PTM 2 Memory Size/Attribute Register (PCILO_PTM2MS) ............................................. 25-197
Figure 25-151. Process ID (PI D) .............................................................................................................. 25-198
Figure 25-152. Programmable Interval Timer (PIT) .................................................................................. 25-199
Figure 25-153. PLB Arbiter Control Register (PLBO_ACR) ...................................................................... 25-200
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PPC405GP User's Manllal Preliminary