IBM PowerPC 405GP User Manual page 398

17.5.2.12 PMM 2 PCI High Address Register (PCILO_PMM2PCIHA)
PCILO_PMM2PCIHA defines the high-order 32 bits of the PCI address generated in response to PLB
access to range 2. See "PMM 0 PCI High Address Register (PCILO_PMMOPCIHA)" on page 17-23.
01
Figure 17-18. PMM 2 PCI High Address Register (PCILO_PMM2PCIHA)
I
31:0
I
PCI High Address
17.5.2.13 PTM 1 Memory Size/Attribute Register (PCILO_PTM1MS)
PCILO_PTM1 MS defines the size and attributes of the of PCI memory region mapped to local (PLB)
space through PTM 1.
~CILO_PTM1
MS affects the operation of PCI PTM 1 BAR.
SIZE
1
31
*
12111
Figure 17-19. PTM 1 Memory Size/Attribute Register (PCILO_PTM1MS)
31 :12 MASK Defines the size of the region of PCI The minimum range size is 4KB. Valid
memory space that is mapped to local ranges are always a, power of 2.
(PLB) space using PTM 1.
For example, a value of OxFFOOOOOO
indicates that the region contains 16MB.
11 :1 Reserved Returns 0 when read.
0 EMM Determines if range 1 is enabled to map
PCI memory space to PLB space.
Always 1 (enabled).
17.5.2.14 PTM 1 Local Address Register (PCILO_PTM1LA)
PCILO_PTM1 LA defines the local (PLB) address that is generated in response to a PCI access to
local (PLB) space through PTM 1. Only bits that are 1 in PCILO_PTM1 MS are passed to the PLB
address. The other (least significant) bits of the PLB address are passed through from the PCI
address. Only bits 31 :12 are writable. Bits 11:0 are always O.
Preliminary PCI Interface
17-27