On-Chip Peripheral Bus; Opb Features - IBM PowerPC 405GP User Manual

4
ALK4 POBO_BEAR Address Lock Master 4
o
Master 4 POBO_BEAR address is
unlocked
1 Master 4 POBO_BEAR address is locked
5:6 PTE5
PLB Timeout Error Status Master 5 Master 5 is DMA.
00 No Master 5 error occurred
01 Master 5 timeout error occurred
10 Master 5 slave error occurred
11 Reserved
7 R/W5 Read/Write Status Master 5
o
Master 5 error operation is a read
1 Master 5 error operation is a write
8 FLK5 POBO_BESR1 Field Lock Master 5
o
Master 5 POBO_BESR1 field is unlocked
1 Master 5 POBO_BESR1 field is locked
9
ALK5 POBO_BEAR Address Lock Master 5
o
Master 5 POBO_BEAR address is
unlocked
1 Master 5 POBO_BEAR address is locked
10:31 Reserved
2.1.7.3 On-Chip Peripheral Bus
The OPB is used to attach peripherals that do not require the bandwidth of the PLB. The OPB does
not connect directly to the PPC405GP processor core, which accesses peripherals attached to the
OPB through a PLB-to-OPB bridge.
2.1.8 OPB Features
The on-chip peripheral bus features:
• A 32-bit address bus and a 32-bit data bus
• Dynamic bus sizing; byte, halfword, and word transfers
• Byte and halfword duplication for byte and halfword transfers
• Single-cycle transfer of data between OPB bus master and OPB slaves
• Sequential address (burst) protocol support
• Devices on the OPB may be memory mapped, act as DMA peripherals, or support both transfer
methods
• A 16-cycle fixed bus timeout provided by the OPB arbiter
• Bus parking for reduced latency
• Bus arbitration overlapped with last cycle of bus transfers
Preliminary
On-Chip Buses . 2-11