Program Interrupt; Table 10-14. Register Settings During Alignment Interrupts; Table 10-15. Esr Usage For Program Interrupts - IBM PowerPC 405GP User Manual

Executing an
rfi
instruction restores the program counter from SRRO and the MSR from SRR1, and
execution resumes at the address in the program counter
Alignment interrupts cannot be disabled. To avoid overwrites of SRRO and SRR1 by alignment
interrupts that occur within a handler, interrupt handlers should save these registers as soon as
possible.
Table 10-14. Register Settings during Alignment Interrupts
SRRO Written with the address of the instruction causing the alignment interrupt
SRR1 Written with the contents of the MSR
MSR WE, EE, PR, OWE, IR, DR
~
0
CE, ME, DE
~
unchanged
PC EVPR[O:15] II Ox0600
DEAR Written with the address that caused the alignment violation
10.18 Program Interrupt
Program interrupts are caused by attempting to execute:
• An illegal instruction
• A privileged instruction while in the problem state
• Executing a trap instruction with conditions satisfied
The ESR bits that differentiate these situations are listed and described in Table 10-15. When a
program interrupt occurs, the appropriate bit is set and the others are cleared. These interrupts are
not maskable.
Table 10-15. ESR Usage for Program Interrupts
Bits Interrupts Cause
ESR[PIL]
Illegal instruction Opcode not recognized
ESR[PPR] Privileged instruction Attempt to use a privileged instruction in the problem state
ESR[PTR] Trap Excepting instruction is a trap
The program interrupt handler does not need to reset the ESR.
When one of the following occurs, the PPC405GP does not execute the instruction, but writes the
address of the excepting instruction into SRRO:
• Attempted execution of a privileged instruction in problem state
• Attempted execution of an illegal instruction (including memory management instructions when
memory management is disabled
Trap instructions can be used as a program interrupt or a debug event, or both (see "Debug Events"
on page 12-16 for information about debug events). When a trap instruction is detected as a program
interrupt, the PPC405GP writes the address of the trap instruction into SRRO. See
tw
on page 24-190
and
twi
on page 24-193 (both in Chapter 24, "Instruction Set") for a detailed discussion of the
behavior of trap instructions with various interrupts enabled.
10-40 PPC405GP User's Manual Preliminary