Shadow Tlb Consistency; Figure 6-3. Itlb/Dtlb/Utlb Address Resolution - IBM PowerPC 405GP User Manual

· Figure 6-3 illustrates the relationship of the shadow TLBs and UTLB in address translation:
Generate I-side
Effective Address
Translation Disabled
(MSR[IR]=O)
Translation Enabled
(MSR[IR]
=
1)
Route Address
to DTLB
Generate D-side
Effective Address
Translation Enabled
(MSR[DR]
=
1)
Translation Disabled
(MSR[DR]
=
0)
I-Side TLB Miss
or
D-Side TLB Miss
Exception
Figure 6-3. ITLB/DTLB/UTLB Address Resolution
6.3.4.2 Shadow TLB Consistency
The processor invalidates the entire ITLB contents when the following context-synchronizing events
occur, to help to maintain ITLB integrity.
• isync instruction
• Processor context switch (all interrupts, rfi, rfci)
6-8 PPC405GP User's Manual Preliminary