Table of Contents
Advertisement
Index
A
AA field
conditional branches 3-35
unconditional branches 3-34
access protection
cache instructions 6-15
string instructions 6-16
virtual mode 6-12
add 24-6
add.
24-6
addc 24-7
addc.
24-7
addco 24-7
addco.
24-7
adde 24-8
adde.
24-8
addeo 24-8
addeo. 24-8
addi 24-9
addic 24-10
addic. 24-11
addis 24-12
addme 24-13
addme.
24-13
addmeo 24-13
addmeo.
24-13
addo 24-6
addo.
24-6
address map
illustrated 3-2
address translation
illustrated 6-2
MMU 6-1
relationship between TLBs, illustrated 6-8
addressing modes
1-11
addze 24-14
addze. 24-14
addzeo 24-14
addzeo. 24-14
alignment
for cache control instructions 3-27
for storage reference instructions 3-27
of data types 3-26
alignment interrupts
causes of 3-28
register settings
10-40
summary 10-39
and 24-15
and. 24-15
andc 24-16
andc. 24-16
andi.
24-17
andis. 24-18
architecture, PowerPC
1-4
arithmetic compares 3-13
arithmetic instructions 3-49
Preliminary
asynchronous interrupts 10-22
B
b 24-19
ba 24-19
bc 24-20
bca 24-20
bcctr 24-26
bcctrl 24-26
bcl 24-20
bcla 24-20
bclr 24-30
bclrl 24-30
bctr 24-27
bctrl 24-27
bdnz 24-21
bdnza 24-21
bdnzf 24-21
bdnzfa 24-21
bdnzfl 24-21
bdnzfla 24-21
bdnzflr 24-31
bdnzflrl 24-31
bdnzl 24-21
bdnzla 24-21
bdnzlr 24-31
bdnzlrl 24-31
bdnzt 24-21
bdnzta 24-21
bdnztl 24-21
bdnztla 24-21
bdnztlr 24-31
bdnztlrl 24-31
bdz 24-21
bdza 24-21
bdzf 24-22
bdzfa 24-22
bdzfl 24-22
bdzfla 24-22
bdzflr 24-31
bdzflrl 24-31
bdzl 24-21
bdzla 24-21
bdzlr 24-31
bdzlrl 24-31
bdzt 24-22
bdzta 24-22
bdztl 24-22
bdztla 24-22
bdztlr 24-31
bdztlrl 24-31
beq 24-22
beqa 24-22
beqctr 24-27
beqctrl 24-27
beql 24-22
beqlr 24-31
Index
X-1
Advertisement
Chapters
Table of Contents
