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Bit assignments for the IICO_MDBUF and IICO_SDBUF are identical, as illustrated in Figure 22-5.
1
0
71
Figure 22-5. IICO Slave Data Buffer (IICO_SDBUF)
0
Data bit
1
Data bit
2
Data bit
3
Data bit
4
Data bit
5
Data bit
6
Data bit
7
Data bit
IICO_SDBUF is cleared (flushed and set to empty) whenever the IIC interface is reset, or
IICO_MDCNTL[FSB] = 1.
22.3.3 IICO Low Master Address Register
The IICO Low Master Address (IICO_LMADR) and IICO High Master Address Register (IICO_HMADR)
form addresses that the IIC interface transmits on the IIC bus.
Programming Note: IICO_HMADR is used only for 10-bit addressing.
When IICO_CNTL[AMD]
=
°
(7-bit addressing), only IICO_LMADR is written. IICO_LMADR[AO:A6]
form the address transmitted on the IIC bus; IICO_LMADR[A7] is a don't care. When
IICO_CNTL[AMD]
=
1 (10-bit addressing), IICO_LMADR[AO:A7] form the second byte address
transmitted on the IIC bus.
Figure 22-6 illustrates the IICO_LMADR.
AD
A2
A4
A6
~
* * *
101112 31
4
1
5
1
6
1
7
1
t t t t
A1
A3
A5
A7
Figure 22-6. IICO Low Master Address Register (IICO_LMADR)
0
AO
Address bit 0
1
A1
Address bit 1
2
A2
Address bit 2
3
A3
Address bit 3
4
A4
Address bit 4
5
AS
Address bit 5
Preliminary
lie
Bus Interface
22-5
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