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Figure 19-19. Receive Mode Register (EMACO_RMR) .............................................................................. 19-29
Figure 19-20. Interrupt Status Register (EMACO_ISR) .............................................................................. 19-31
Figure 19-21. Interrupt Status Register (EMACO_ISER) ............................................................................ 19-33
Figure 19-22. Individual Address High Register (EMACO_IAHR) ............................................................... 19-35
Figure 19-23. Individual Address Low Register (EMACO_IALR) ................................................................ 19-36
Figure 19-24. VLAN TPID Register (EMACO_VTPID) ................................................................................ 19-36
Figure 19-25. VLAN TCI Register (EMACO_ VTCI) ..................................................................................... 19-37
Figure 19-26. Pause Timer Register (EMACO_PTR) ................................................................................. 19-37
Figure 19-27. Individual Address Hash Tables 1-4 (EMACO_IAHT1-EMACO_IAHT4) ............................. 19-37
Figure 19-28. Group Address Hash Tables 1-4 (EMACO_GAHT1-EMACO_GAHT4) ............................... 19-38
Figure 19-29. Last Source Address High Register (EMACO_LSAH) .......................................................... 19-38
Figure 19·30. Last Source Address Low Register (EMACO_LSAL) ........................................................... 19-38
Figure 19-31. inter-Packet Gap Value Register (EMACO_IPGVR) ............................................................. 19-39
Figure 19-32. STA Control Register (EMACO_STACR) ............................................................................. 19-39
Figure 19-33. Transmit Request Threshold Register (EMACO_ TRTR) ...................................................... 19-41
Figure 19-34. Receive Low/High Water Mark Register (EMACO_RWMR) ................................................. 19-42
Figure 19-35.
Number of Octets Transmitted (EMACO_OCTX) ................................................................ 19-42
Figure 19-36.
Number of Octets Received (EMACO_OCRX) .................................................................... 19-42
Figure 19-37. Management Interface with PHY ......................................................................................... 19-43
Figure 19-38. EMAC-MAL Communication Phases ................................................................................... 19-44
Figure 20-1. General PPC405GP Structure (Overview) ............................................................................... 20-2
Figure 20-2. MAL Internal Structure ............................................................................................................. 20-3
Figure 20-3. Transmit Operation .................................................................................................................. 20-5
Figure 20-4. Receive Operation ................................................................................................................... 20-6
Figure 20-5. Buffer Descriptor Structure ....................................................................................................... 20-8
Figure 20-6. Packet Memory Structure ......................................................................................................... 20-9
Figure 20-7. TX Status/Control Field .......................................................................................................... 20-15
Figure 20-8. RX Status/Control Field .......................................................................................................... 20-16
Figure 20-9. Error Status Register Field ..................................................................................................... 20-21
Figure 20-10. MAL Error Processing .......................................................................................................... 20-23
Figure 20-11. MAL Configuration Register (MALO_CFG) ........................................................................... 20-25
Figure 20-12. TX ChanneLActive Set Register (MALO_ TXCASR) ............................................................ 20-27
Figure 20-13. TX ChanneLActive Reset Register (MALO_ TXCARR) ........................................................ 20-27
Figure 20-14. RX ChanneLActive Set Register (MALO_RXCASR) ........................................................... 20-27
Figure 20-15. RX Channel_Active Reset Register (MALO_RXCARR) ....................................................... 20-28
Figure 20-16. TX End of Buffer Interrupt Status Register (MALO_ TXEOBISR) .......................................... 20-28
Figure 20-17. RX. End of Buffer Interrupt Status Register (MALO_RXEOBISR) ......................................... 20-29
Figure 20-18. MAL Error Status Register (MALO_ESR) ............................................................................. 20-30
Figure 20-19. MAL Interrupt Enable Register (MALO_IER) ........................................................................ 20-31
Figure 20-20. TX Descriptor Error Interrupt Register (MALO_ TXDEIR) ..................................................... 20-32
Figure 20-21. RX Descriptor Error Interrupt Register (MALO_RXDEIR) ..................................................... 20-32
Figure 20-22. TX Channel Table Pointer x Register (MALO_ TXCTPxR) .................................................... 20-33
Figure 20-23. RX Channel Table Pointer x Register (MALO_RXCTPxR) ................................................... 20-33
Figure 21-1. UART Receiver Buffer Registers (UARTx_RBR) ..................................................................... 21-5
Figure 21-2. UART Transmitter Holding Registers (UARTx_ THR) .............................................................. 21-5
Figure 21-3. UART Interrupt Enable Registers (UARTx_IER) ...................................................................... 21-5
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PPC405GP User's Manual
Preliminary
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