Ocm Programming Guidelines - IBM PowerPC 405GP User Manual

bits defines a 64MB address space. The instruction side and data side can share a 64MB address
space, or each can have its own 64MB address space. The address spaces are fully relocatable on
64MB boundaries within the 4GB address space of the PPC405GP, but the programmer must assign
OCM address space to avoid conflicts with other assigned addresses. See "Programming Model" on
page 3-1 for information about the PPC405GP memory map.
OCM Address Space OCMSRAM
1
0
*
19
1
20
*
31
1
Figure 5-1.
O.eM
Address Usage
Figure 5-1 illustrates OCM address usage. The OCM SRAM array size is 4KB. Address bits 20:31
select byte addresses for data-side accesses. Address bits 30:31 are ignored for instruction-side
accesses, because instruction-side accesses return either one or two words per transfer.
Note that the instruction-side and data-side OCM address spaces overlap physically, even if defined
as distinct logical address spaces, because the 4KB SRAM is shared. There is no distinction between
data space or instruction space, except as defined by the programmer.
Addresses in the OCM array are aliased throughout the 'larger OCM address spaces. The larger OCM
address spaces are filled with multiple images of the 4KB SRAM. Aliased addresses refer to the same
physical memory locations.
Programming Note: To avoid possible memory coherency problems when using aliased
addresses, align aliased addresses on 16KB boundaries rather than on 4KB boundaries. See
"Store Data Bypass Behavior and Memory Coherency" on page 5-3 for details.
If address translation is enabled (MSR[IR, DR]
=
1), one or more TLB entries for the OCM address
space must exist to validate accesses. However, the virtual addresses are
not
translated, and 32-bit
effective addresses (virtual addresses) are presented to OCM.
Data-side OCM contents can use big end ian or little end ian byte ordering. Instruction-side OCM
contents
must
use big endian byte ordering. See "Byte Ordering" on page 3-28 for detailed
information about byte ordering.
5.2
OeM Programming Guidelines
The following guidelines prevent potential problems associated with using OCM:
• Code that uses mtdcr to disable instruction-side OCM access should not run out of the instruction-
side OCM.
Instructions following an mtdcr are not guaranteed to be fetched before the instruction-side OCM
is disabled.
• Do not change the value in OCMO_ISARC while fetching from the instruction-side OCM.
• To change the value in OCMO_ISARC or OCMO_DSARC:
1. Set OCMO_ISCNTL[ISEN]
=
°
to disable instruction-side OCM accesses, or set
OCMO_DSCNTL[DSEN] =
°
to disable data-side OCM accesses.
5-2 PPC405GP User's Manual Preliminary