IBM PowerPC 405GP User Manual page 568

20.3 Buffer Descriptor Overview
The software interface for buffer descriptor (BD) processing consists of a set of registers within MAL
and a set of circular queues in memory. Each transmit and receive COMMAC channel has a
descriptor table that contains buffer location and status information allocated to the channel.
Note: Since MAL uses a flat addressing scheme on the PLB, the physical memory that holds
descriptor tables and buffers can be allocated anywhere in the address space where memory
is possible. Also, it is not necessary to place buffer descriptor tables and buffers in the same
physical memory.
During its operation, MAL is able to modify the contents of memory directly without processor core
knowledge. If the processor core does not provide hardware enforced data cache coherency or data
cache snooping (the PPC405 CPU core does not), data cache coherency is the responsibility of the
software device driver. To simplify device driver software, the MAL buffer descriptor tables should be
placed in non-cached memory when possible. If this is not possible, the software driver must maintain
cache coherency of the buffer descriptor tables by performing data cache flushes or invalidates when
appropriate. When descriptors are in cached memory, the driver software must be aware that multiple
descriptors are present in a single cache line and that cache invalidate or flush operations will be
performed on multiple descriptors at the same time. This is significant because a cache line flush
done by the driver to force a descriptor from the data cache to physical memory could corrupt another
descriptor that occupies the same data cache line and is simultaneously being updated in physical
memory by MAL.
Data buffers, in contrast, should be placed in cachable memory if possible. The software driver can
easily maintain cache coherency of data buffers if:
• All buffers are aligned on a data cache line boundary
• All buffers are a multiple ofa data cache line in size
Note: The data cache line size and alignment in the PPC405GP is 32 bytes.
Before using a received packet, the software driver must invalidate the memory occupied by the buffer
in the data cache for the length specified in the RX buffer descriptor data length field. Before
transmitting a packet the software driver must flush the data buffer from the data cache before setting
the Ready bit in the TX buffer descriptor.
The software device driver fills the buffers pOinted to by transmit buffer descriptors with packets to be
transmitted, and/or provides empty buffers pointed to by receive buffer descriptors to be filled with
received packets. Meanwhile, the hardware processes the descriptors, transfers the packet data
to/from the COMMAC, and updates the status fields of the descriptors.
Each individual transmit or receive channel has its own buffer descriptor table. They are managed
independently of each other. This section describes the individual transmit and receive interfaces.
Packet data associated with each transmit or receive channel is stored in buffers. Each buffer has an
entry dedicated to it in one of the channel's buffer descriptor tables. MAL has a Channel Table Pointer
Register for each of its channels. The COMMAC (EMAC in the PPC405GP) device driver sets the
contents of these registers to point to the starting address of the buffer descriptor table for the
associated channel.
Note: Buffer descriptor tables must start on a 4-KB boundary.
Preliminary Memory Access Layer 20-7