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and ITLB 6-8
context synchronization, example 3-45
ITLB (instruction translation lookaside buffer)
accesses 6-6
L
consistency 6-8
defined 6-6
miss interrupts 6-10,
10-44
programming note 6-9
Ibz 24-71
Ibzu 24-72
Ibzx 24-74
least-recently-used policy. See LRU
Iha 24-75
Ihau 24-76
Ihax 24-78
Ihbrx 24-79
1hz 24-80
Ihzu 24-81
Ihzux 24-82
Ihzx 24-83
Ii 24-9
line control register
description 21-8
line status register 21-11
Link Register. See LR
lis 24-12
little end ian
alignment 3-27
byte ordering supported 3-30
defined 3-28
mapping 3-30
storage attributes 3-30
storage regions
accessing data from 3-31
byte-reverse instructions 3-32- 3-33
fetching instructions from 3-31
Imw 24-84
load strategies, controlled by DCU 4-7
logical compares 3-13
logical instructions
CR 3-50
overview 3-49
LR 25-116
LR (Link Register)
branch instructions 3-51
function 3-8
LRU (Ieast-recently-used) policy
DCU 4-6
ICU 4-2
Iswi 24-85
Iswx 24-87
Iwarx 24-89
Iwz 24-91
Iwzu 24-92
Iwzux 24-93
Iwzx 24-94
M
macchw 24-95
macchws 24-96
X-12
PPC405GP User's Manual
macchwsu 24-97
macchwu 24-98
machhw 24-99
machhwsu 24-101
machhwu 24-102
machine check interrupts
causes 10-35
defined 10-23
machine check-instruction interrupts
handling 10-35
register settings 10-36
synchronism 10-24
Machine State Register. See MSR
maclhw 24-103
maclhws 24-104, 24-138
maclhwu 24-106
MALO_CFG 25-117
MALO_ESR 25-119
MALO_IER 25-121
MALO_RCBSO 25-122
MALO_RXCARR 25-123
MALO_RXCASR 25-124
MALO_RXCTPOR 25-125
MALO_RXDEIR 25-126
MALO_RXEOBISR 25-127
MALO_TXCASR 25-129
MALO_TXCTPOR 25-130
MALO_TXCTP1R 25-130
MALO_TXDEIR 25-131
MALO_TXEOBISR 25-132
mapping
big endian 3-29
little endian 3-30
structure, examples 3-29
mcrf 24-107
mcrxr 24-108
Memory Controller Address Register. See
SDRAMO CFGADDR
Memory Controller Data Register. See
SDRAMO_CFGDATA
memory interface
bus attachment
alternative 16-3
external bus master 16-17
SRAM
burst mode 16-8
bus timeout error 16-11
device-paced transfers 16-11
timing 15-1, 16-2
memory map
address space usage 3-2
PCI configuration registers 25-13
memory mapping
.
of hardware 3-40
memory models, non-supported 4-7, 6-5
memory organization 3-1
memory-mapped inpuVoutput registers. See MMIO
registers
mfcr 24-109
mfdcr 24-110
mfmsr 24-111
Preliminary
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