Multiplexed Ii0S; Driver Enables - IBM PowerPC 405GP User Manual

Embedded processor
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byte
2/byte
3 lane, and accessed using halfword loads and stores. External logic may be required to
develop additional control signals if the data bus is utilized in this manner.
PerAddrO:31
PerCSO:7
PerDataO:7
PerParO
PerWBEO[PerBEO)
PerData8:15
PerPar1
PerWBE1[PerBE1)
PerData 16:23
PerPar2
PerWBE2[PerBE2)
PerData24:31
PerPar3
PerWBE3[PerBE3)
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Figure
16-2.
Attachment of Devices of Various Widths to the Peripheral Data Bus
16.1.2 Multiplexed II0s
Seven of the chip select outputs, PerCS1 :7, are multiplexed with GPIOs, while PerWE is multiplexed
with PCIINT. The multiplexing of these I/0s occurs outside of the EBC logic, see "Pin Sharing" on
page 9-3 for additional details. As a result, software can still configure and attempt to use a peripheral
memory bank whose output is set up as a GPIO. Doing so causes an EBC transaction without an
active chip select and the results are therefore undefined.
In the remainder of this chapter PerCSO:7 and PerWE are assumed to be configured as EBC outputs.
16.1.3 Driver Enables
As shown in Table 16-2, "Effect of Driver Enable Programming on EBC Signal States:' on page 16-5,
the output enables for the peripheral address, data and most of the EBC control signals are
configurable. For systems that do not use an external master or where the external master does not
directly control devices on the peripheral bus, setting EBCO_CFG[CSTC]=1 eliminates the need for
pull-up resistors on PerCSO:7. Pullups are also unnecessary on the remainder of the EBC control
signals when EBCO_CFG[EBTC]=1.
Both chip and system resets set EBCO_CFG[EBTC]=1 and EBCO_CFG[CSTC]=1. In most
applications, clearing EBCO_CFG[CSTC] is not recommended. If EBCO_CFG[EBTC]=O, EBC control
16-4
PPC405GP User's Manual

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