Indirectly Accessed Dcrs; Indirect Access Of Sdram Controller Dcrs; Table 3-7. Sdram Controller Dcr Usage; Table 3-8. Offsets For Sdram Controller Registers - IBM PowerPC 405GP User Manual

3.3.6.2 Indirectly Accessed DCRs
The DCRs for the SDRAM controller, external bus controller (ESC), and decompression controller are
indirectly accessed.
3.3.7 Indirect Access of SDRAM Controller DCRs
The following procedure accesses the SDRAM controller DCRs listed in Table 3-7.
1. Write the offset from Table 3-8 to the Memory Controller Address Register (SDRAMO_CFGADDR).
2. Read data from or write data to the Memory Controller Data Register (SDRAMO_CFGDATA).
Table 3-7. SDRAM Controller DCR Usage
DCR
Register Number Access Description
SDRAMO_CFGADDR Ox010 RIW Memory Controller Address Register
SDRAMO_CFGDATA Ox011 RIW Memory Controller Data Register
Table 3-8. Offsets for SDRAM Controller Registers
Register Offset
RIW Description
SDRAMO_BESRO OxOO R/Clear Bus Error Syndrome Register 0
SDRAMO_BESR1 Ox08 R/Clear Bus Error Syndrome Register 1
SDRAMO_BEAR Ox10 RIW Bus Error Address Register
SDRAMO_CFG Ox20 RIW Memory Controller Options 1
SDRAMO_RTR
Dx30 RIW
Refresh Timer Register
SDRAMO_PMIT Ox34 RIW Power Management Idle Timer
SDRAMO_BOCR Ox40 RIW Memory Bank 0 Configuration Register
SDRAMO_B1CR Ox44
RIW
Memory Bank 1 Configuration Register
SDRAMO_B2CR Ox48
RIW
Memory Bank 2 Configuration Register
SDRAMO_B3CR Dx4C RIW Memory Bank 3 Configuration Register
SDRAMO_TR Ox8D RIW SDRAM Timing Register 1
SDRAMD_ECCCFG Ox94 RIW ECC Configuration
SDRAMO_ECCESR
Ox98 R
ECC Error Status Register
Preliminary Programming Model
3-19