IBM PowerPC 405GP User Manual page 40

Figure 25-154. PLB Error Address Register (PLBO_BEAR) ..................................................................... 25-201
Figure 25-155. PLB Error Status Register (PLBO_BESR) ........................................................................ 25-202
Figure 25-156. Bridge Error Address Register (POBO_BEAR) ................................................................. 25-204
Figure 25-157. Bridge Error Status Register 0 (POBO_BESRO) ............................................................... 25-205
Figure 25-158. Bridge Error Status Register 1 (POBO_BESR1) ............................................................... 25-207
Figure 25-159. Processor Version Register (PVR) ................................................................................... 25-208
Figure 25-160. Memory Bank 0-3 Configuration Registers (SDRAMO_BOCR-SDRAMO_B3CR) ........... 25-209
Figure 25-161. Bus Error Address Register (SDRAMO_BEAR) ................................................................ 25-210
Figure 25-162. Bus Error Syndrome Register 0 (SDRAMO_BESRO) ....................................................... 25-211
Figure 25-163. Bus Error Status Register 1 (SDRAMO_BESR1) .............................................................. 25-213
Figure 25-164. Memory Controller Configuration (SDRAMO_CFG) .......................................................... 25-214
Figure 25-165. ECC Configuration Register (SDRAMO_ECCCFG) .......................................................... 25-218
Figure 25-166. ECC Error Status Register (SDRAMO_ECCESR)- ............................................................ 25-219
Figure 25-167. Power Management Idle Timer (SDRAMO_PMIT) ........................................................... 25-220
Figure 25-168. Refresh Timing Register (SDRAMO_RTR) ....................................................................... 25-221
Figure 25-169. SDRAM Timing Register (SDRAMO_TR) ......................................................................... 25-222
Figure 25-170. Storage Guarded Register (SGR) .................................................................................... 25-224
Figure 25-171. Storage Little-Endian Register (SLER) ............................................................................. 25-226
Figure 25-172. Special Purpose Registers General (SPRGO-SPRG7) .................................................... 25-228
Figure 25-173. Save/Restore Register 0 (SRRO) ..................................................................................... 25-229
Figure 25-174. Save/Restore Register 1 (SRR1) ..................................................................................... 25-230
Figure 25-175. Save/Restore Register 2 (SRR2) ..................................................................................... 25-231
Figure 25-176. Save/Restore Register 3 (SRR3) ..................................................................................... 25-232
Figure 25-177. Storage User-defined 0 Register (SUOR) ......................................................................... 25-233
Figure 25-178. Time Base Lower (TBL) .................................................................................................... 25-235
Figure 25-179. Time Base Upper (TBU) ................................................................................................... 25-236
Figure 25-180. Timer Control Register (TCR) ........................................................................................... 25-237
Figure 25-181. Timer Status Register (TSR) ............................................................................................ 25-238
Figure 25-182. UART Baud-Rate Divisor Latch (LSB) Registers (UARTx_DLL) ...................................... 25-239
Figure 25-183. UART Baud-Rate Divisor Latch (MSB) Registers (UARTx_DLM) .................................... 25-240
Figure 25-184. UART FIFO Control Registers (UARTx_FCR) ................................................................. 25-241
Figure 25-185. UART Interrupt Enable Registers (UARTx_IER) .............................................................. 25-242
Figure 25-186. UART Interrupt Identification Registers (UARTx_1I R) ...................................................... 25-243
Figure 25-187. UART Line Control Registers (UARTx_LCR) ................................................................... 25-244
Figure 25-188. UART Line Status Registers (UARTx_LSR) ........................................... ; ......................... 25-245
Figure 25-189. UART Modem Control Registers (UARTx_MCR) ............................................................. 25-247
Figure 25-190. UART Modem Status Registers (UARTx_MSR) .............................................................. 25-248
Figure 25-191. UART Receiver Buffer Registers (UARTx_RBR) ............................................................. 25-249
Figure 25-192. Scratch pad Registers (UARTx_SCR) ....... : ....................................................................... 25-250
Figure 25-193. UART Transmitter Holding Registers (UARTx_ THR) ....................................................... 25-251
Figure 25-194. UIC Critical Register (UICO_CR) ...................................................................................... 25-252
Figure 25-195. UIC Enable Register (UICO_ER) ...................................................................................... 25-255
Figure 25-196. UIC Masked Status Register (UICO_MSR) ....................................................................... 25-258
Figure 25-197. UIC Polarity Register (UICO_PR) ..................................................................................... 25-261
Figure 25-198. UIC Status Register (UICO_SR) ....................................................................................... 25-264
Figure 25-199. UIC Trigger Register (UICO_ TR) ...................................................................................... 25-267
Preliminary Figures
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