Pll Mode Register (Cpco_Pllmr) - IBM PowerPC 405GP User Manual

7.7.1 . PLL Mode Register (CPCO_PLLMR)
The read-only CPCO_PLLMR contains a number of PLL and clock divisor values.
CPCO_PLLMR fields are based on the external strapping options.
The CPCO_PLLMR is big endian. However, values returned for the CPCO_PLLMR[FWDV, FBDV,
TUN] fields are little end ian to enable easier comparison of these bits with the PLL documentation in
ASIC SA-12E Databook (available from your IBM representative), which uses little endian formats.
FWDV
TUN
OPDV
EPDV
31
Figure 7-2. PLL Mode Register (CPCO_PLLMR)
0:2 FWDV Forward Divisor
PLLOUTA Value:
000 Forward divisor is 8. 50 MHz-100 MHz
001 Forward divisor is 7.
58 MHz-114 MHz
010 Forward divisor is 6. 66 MHz-134 MHz
011 Forward divisor is 5. 80 MHz-160 MHz
100 Forward divisor is 4. 100 MHz-200 MHz
101 Forward divisor is 3. 133 MHz-267 MHz
110 Forward divisor is 2. 200 MHz-400 MHz
111 Forward divisor is 1. 400 MHz-800 MHz
Note: PLLOUTA is the CPU clock in
PPC405GP.
3:6 FBDV Feedback Divisor
0000 Feedback divisor is 16.
0001 Feedback divisor is 1.
0010 Feedback divisor is 2.
0011 Feedback divisor is 3.
0100 Feedback divisor is 4.
0101 Feedback divisor is 5.
0110 Feedback divisor is 6.
0111 Feedback divisor is 7.
1000 Feedback divisor is 8.
1001 Feedback divisor is 9.
1010 Feedback divisor is 10.
1011 Feedback divisor is 11.
1100 Feedback divisor is 12.
1101 Feedback divisor is 13.
1110 Feedback divisor is 14.
1111 Feedback divisor is 15.
7-10 PPC405GP User's Manual Preliminary