Alignment For Storage Reference And Cache Control Instructions; Alignment And Endian Operation - IBM PowerPC 405GP User Manual

3.4.1 Alignment for Storage Reference and Cache Control Instructions
The storage reference instructions (loads and stores; see Table 3-23, "Storage Reference
Instructions:' on page 3-48) move data to and from storage. The data cache control instructions listed
in Table 3-32, "Cache Management Instructions:' on page 3-52, control the contents and operation of
the data cache unit (DCU). Both types of instructions form an effective address (EA). The method of
calculating the EA for the storage reference and cache control instructions is detailed in the
description of those instructions. See Chapter 24, "Instruction Set:' for more information.
Cache control instructions ignore the four least significant bits of the EA; no alignment restrictions
exist in the DCU because of EAs. However, storage control attributes can cause alignment
exceptions. When data address translation is disabled and a dcbz instruction references a storage
region that is non-cachable, or for which write-through caching is the write strategy, an alignment
exception is taken. Such exceptions result from the storage control attributes, not from EA alignment.
The alignment exception enables system software to emulate the write-through function.
Alignment requirements for the storage reference instruct:ons and the dcread instruction depend on
the particular instruction. Table 3-16, "Alignment Exception Summary," on page 3-28, summarizes the
instructions that cause alignment exceptions.
The data targets of instructions are of types that depend upon the instruction. The load/store
instructions have the following "natural" alignments:
• Load/store word instructions have word targets, word-aligned.
• Load/ store halfword instructions have halfword targets, halfword-aligned.
• Load/store byte instructions have byte targets, byte-aligned (that is, any alignment).
Misalignments are addresses that are not naturally aligned on data type boundaries. An address not
divisible by four is misaligned with respect to word instructions. An address not divisible by two is
misaligned with respect to halfword instructions. The PPC405GP implementation handles
misalignments within and across word boundaries, but there is a perforll1ance penalty because
additional bus cycles are required.
3.4.2 Alignment and Endian Operation
The end ian storage control attribute does not affect alignment behavior. In little endian storage
regions, the alignment of data is treated as it is in big end ian storage regions; no special alignment
exceptions occur when accessing data in little end ian storage regions. Note that the alignment
exceptions that apply to big end ian region accesses also apply to little end ian storage region
accesses.
Preliminary Programming Model
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