Changing Power States - IBM PowerPC 405GP User Manual

17.8.3 Changing Power States
The PCI bridge has two registers that control changing the power state. The host requests a change
in the power state by writing to the PCICO_PMCSR. The other register is PCICO_PMSCRR), which
provides a method of informing the local processor of a state change request and of preventing
completion of the write to the PCICO_PMCSR until the local processor indicates that it is ready for the
state change.
Power state changes are handled as follows:
• If a host write to PCICO_PMCSR requests an unsupported state change (such as a change to D2),
the write is accepted but is ignored (no state change occurs).
• If a host write to PCICO_PMCSR requests a change from D3hot to DO, the write is accepted. Then,
the PCI bridge asserts the power management reset signal, which causes the entire SOC to be
reset.
Note: The PCI bridge assumes that any requested state change from D3hot is always to DO.
• All other change requests are handled with the following sequence:
1.The host requests a new power state by a PCI write to the PCICO_PMCSR.
2.The host PCI write is retried (unless PCICO_PMSCRR[DWE]
=
0).
3.The host PCI write (retried or not) sets PCICO_PMSCRR[SCR]
=
1, which drives an interrupt to
the local processor.
4.The local processor recognizes the interrupt. The local processor checks
PCICO_PMSCRR[SCR, REQST] to determine the nature of the request.
S.The local processor proceeds to power down the subsystem if the requested state is valid.
6.When the subsystem has been powered down and is ready to change state, the local processor
clears the PCICO_PMSCRR[SCR] and sets PCICO_PMSCRR[APW]
=
1.
7.When the host PCI write reoccurs:
- It is accepted.
- PCICO_PMSCR is updated (only if the transition is valid).
- PCICO_PMSCRR[APW]
=
0, unless PCICO_PMSCRR[DWE] = 0, in which case
PCICO_PMSCRR[APW]
=
1 always.
- The PCI bridge enters a new power state.
The PCI bridge operates with the clock power management (CPM) logic to enable the bridge to be put
into sleep mode under control of software. See Chapter 13, "Clock and Power Management" for
discussion of the CPM function.
17-60 PPC405GP User's Manual Preliminary