IBM PowerPC 405GP User Manual page 617

22.1.2 Seven-Bit Addresses
Figure 22-1 illustrates a 7-bit address. For master transfers, the address bits 0 through 6 (AO:A6) are
read from IICO_LMADR. For slave transfers, AO:A6 are read from IICO_LSADR. Bit 7 of address byte
o
contains a transfer type bit provided by the IIC interface.
MSb LSb
Address Byte 0
I
AO A 1 A2 A3 A4 A5 A6
I
RIW
I
~B=i~tO~------------------~--~~B=it~7~
Figure 22-1. 7-Bit Addressing
22.1.3 Ten-Bit Addresses
Figure 22-2 illustrates a 10-bit address. AO:A1 of address byte 0 are read from IICO_HMADR[A6:A7]
(for master transfers) or IICO_HSADR[A6:A7] (for slave transfers). These are the two highest-order
address bits transmitted on the IIC bus. Bit 7 of address byte 0 contains a transfer type bit provided by
the IIC interface.
For 1 O-bit addressing for master or slave transfers, respectively, IICO_HMADR[AO:A4] and
IICO_HSADR [AO:A4] must contain Ob11110.
The low-order byte of the 10-bit address, contained in AO:A7 of address byte 1, are read from
IICO_LMADR or IICO_LSADR for master or slave transfers, respectively.
MSb LSb
Address Byte 0
I
1 0 AO A1
I
RIW
I
~B=i~tO~------------------~--~~B=it~7~
MSb LSb
Address Byte 1
I
A2 A3 A4 A5 A6
A7 A8
I
A9
I
Bit 0
Bit 7
Figure 22-2. 1 O-Bit Addressing
22.2
lie
Registers
IIC registers are accessed at memory locations OxEF600500-0xEF600510 in the PPC405GP.
Table 22-1 lists the IIC registers. Descriptions of the registers, in the listed order, follow in "IIC
Register Descriptions" on page 22-3.
Table 22-1.
lie
Registers
PPC40SGP
Effect of
Register Mnemonic Memory Map Address Access Reset
IICO Master Data Buffer IICO_MDBUF
OxEF60 0500 OxO RIW
Cleared
Reserved OxEF60 0501 Ox1
22-2
PPC405GP Usei's Manual Prelirninary
Bits
8,16