Arbitration Between Tx Channels; Independent Mode; Dependent Mode - IBM PowerPC 405GP User Manual

19.3.1 Arbitration Between TX Channels
Because both EMAC transmit channels (referred to as TX Channel
°
and TX Channel 1) drive data
into the same FIFO, they cannot request packet data from MAL at the same time. MAL ensures that
only one EMAC transmit channel is active at a given time.
19.3.2 Independent Mode
In this mode, each EMAC transmit channel independently requests packets from MAL. Each channel
can be configured to work in single packet or multiple packet modes.
In single packet mode, EMACO_MR1 [TRO]
=
00 and EMACO_MR1 [TR1]
=
00. The channel requests
one packet from MAL and resets EMACO_TMRO[GNPO, GNP1] as appropriate. The channel asks for
service again only after EMACO_ TMRO[GNPO]
=
1 or EMACO_ TMRO[GNP1]
=
1 (set by the device
driver).
In multiple packet mode, EMACO_MR1 [TRO]
=
01 and EMACO_MR1 [TR1]
=
01. After the channel
finishes transferring a packet, the channel asks MAL for the next packet as soon as the other channel
is in its Idle Phase and there is enough room in the FIFO. The channel continues to request more
packets until one of the following events occur:
• The channel receives notification from MAL that the next buffer descriptor is not marked ready for
transmission. When this occurs, the channel sets EMACO_ TMRO[GNPO, GNP1] = 0, as
appropriate, and waits for software to reactivate it by setting EMACO_ TMRO[GNPO] = 1 or
EMACO_ TMRO[GNP1]
=
1.
• A transmit error or signal quality error (SQE) occurs and the corresponding interrupt is not masked
in the EMACO_ISER. After such an error, the channel sets EMACO_ TMRO[GNPO, GNP1]
=
0, as
appropriate, and sets EMACO_ISR[DBO]
=
1 or EMACO_ISR[DB1]
=
1 (the EMACO_ISR field that
is set depends on which channel is active) and the corresponding EMACO_ISR error. The channel
does not request service again until EMACO_TMRO[GNPO]
=
1 or EMACO_TMRO[GNP1]
=
1 and
EMACO_ISR[DBO]
=
°
or EMACO_ISR[DB1]
=
°
(again, depending on channel).
In independent mode, if both channels are configured to work in multiple packet mode and both
EMACO_TMRO[GNPO]
=
1 and EMACO_TMRO[GNP1]
=
1 at the same time, the channels operate in
a sequential repeating manner as long as no errors occur.
19.3.3 Dependent Mode
In dependent mode, EMACO_MR1 [TRO]
=
10 and EMACO_MR1 [TR1]
=
10. The two TX channels act
as if they were one channel, sharing EMACO_ TMRO[GNPD]. When EMACO_ TMRO[GNPD]
=
1, the
channel specified by EMACO_ TMRO[FC] starts requesting MAL service. Then, both channels
continue to request packets from MAL in an alternating, sequential, repeating manner, until one of the
following occurs:
• One of the channels receives notification from MAL that the next buffer descriptor is not marked
ready for transmission. When this occurs, EMAC clears EMACO_ TMRO[GNPD]. At this point,
neither channel requests a packet from MAL until EMACO_ TMRO[GNPD] back to 1. The first
channel to request a new packet from MAL when this occurs is the channel that received
notification from MAL that no packets were ready to transmit (regardless of the setting of
EMACO_ TMRO[FC]). Further requests continue in an alternating, repeating manner.
19-6 PPC405GP User's Manual Preliminary