IBM PowerPC 405GP User Manual page 626

6
IRQA IRQ Active
To clear IICO_STS[IRQA], set
o
No IIC interrupt has been sent to the
IICO_STS[IRQA]
=
1.
universal interrupt controller (UIC).
If IICO_MDCNTL[EINT]
=
0, then
1 An IIC interrupt has been sent to the UIC.
IICO_STS[IRQA] is not set.
7 PT
Pending Transfer Read-only.
o
No transfer is pending, or transfer is in
progress.
1 Transfer is pending.
The Error and Pending Transfer, IICO_STS[ERR, PT], bit fields indicate the success or failure of the
requested transfer. Table 22-3 interprets the transfer status for all possible combinations of the
IICO_STS[ERR,PT] bit fields.
Table 22-3. IICO_STS[ERR, PT] Decoding
ERR PT
Status
0
0
Requested transfer completed without errors
0 1
Requested transfer is in progress; no errors were detected
1 0
Requested transfer is complete, but not all data was transferred
1 1
Requested transfer is in progress; but an error was detected
Programming Note: Software should not take any action regarding a master transfer unless all
pending transfers are completed, IICO_STS[PT] = 0.
If an error requires the IIC interface to send a Stop, the Stop Complete bit field is set,
IICO_STS[SCMP]
=
1. Note that slave operations should be serviced regardless of the state of a
requested master transfer.
The IIC interface is placed in sleep mode by setting the CPCO_ER[IIC] via software. Awaking the IIC
interface is possible directly through software by clearing the CPCO_ER[IIC] or indirectly by detecting
a Start condition on the IIC bus. When a Start condition is detected, the IIC interface is awakened,
clearing the CPCO_ER[IIC] and the IICO_STS[SLPR].
The IICO_STS[MDBS, MDBF] contain the current status of the Master Data Buffer, IICO_MDBUF.
When the IICO_MDBUF contains data, IICO_STS[MDBS] is set. When the IICO_MDBUF is full,
IICO_STS[MDBF] is set.
The state of the IICO_MDBUF is not instantly recorded by the IICO_STS[MDBS, MDBF]. The delay
depends on the size of the buffer access. For halfword accesses, these fields are valid on the third
OPB clock following the transfer. For byte accesses, these fields are valid on the second OPB clock
following the transfer.
22.3.8 IICO Extended Status Register
The IICO Extended Status register (IICO_EXTSTS) reports additional IIC status.
During and after transfers, software can read the IICO_STS and IICO_EXTSTS registers to determine
the state of the IIC interface and the IIC bus.
Figure 22-11 illustrates the IICO_EXTSTS.
Preliminary
IIC Bus Interface
22-11