Instruction Tlb Miss Interrupt; Debug Interrupt; Table 10-22. Register Settings During Instruction Tlb Miss Interrupts - IBM PowerPC 405GP User Manual

Table 10-21. Register Settings during Data TLB Miss Interrupts (continued)
MSR WE, EE, PR, DWE, IR, DR
f -
0
CE, ME, DE
f-
unchanged
PC EVPR[0:15] II Ox11 00
DEAR Set to the effective address of the failed access
ESR
DST
f-
1 if excepting operation is a store operation (includes debl, debz,
and deeei).
MCI
f-
unchanged
All other bits are cleared.
Programming Note: Data TLB miss interrupts can happen whenever data translation is enabled.
Therefore, ensure that SRRO and SRR1 are saved before enabling translation in an interrupt
handler.
10.24 Instruction TLB Miss Interrupt
The instruction TLB miss interrupt is generated if instruction translation is enabled and execution is
attempted for an instruction for which a valid TLB entry matching the EA and PID for the instruction
fetch is not present. The instruction whose fetch caused the TLB miss is saved in SRRO.
The interrupt is precise with respect to the attempted execution of the instruction. Program flow
vectors to EVPR[0:15 " Ox1200.
The following are modified to the values specified in Table 10-22
Table 10-22. Register Settings during Instruction TLB Miss Interrupts
SRRO Set to the address of the instruction for which no valid translation exists.
SRR1 Set to the value of the MSR at the time of the interrupt
MSR AP, APE, WE, EE, PR, DWE, IR, DR
f-
0
CE, ME, DE
f-
unchanged
PC EVPR[O: 15] II Ox1200
Programming Note: Instruction TLB miss interrupts can happen whenever instruction translation
is active. Therefore, insure that SRRO and SRR1 are saved before enabling translation in an
interrupt handler.
10.25 Debug Interrupt
Debug interrupts can be either synchronous or asynchronous. These debug events generate
synchronous interrupts: branch taken (BT), data address compare (DAC), data value compare (DVC),
instruction address compare (lAC), instruction completion (IC), and trap instruction (TIE). The
exception (EXC) and unconditional (UDE) debug events generate asynchronous interrupts. See
"Debug Events" on page 12-16 for more information about debug events.
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