IBM PowerPC 405GP User Manual page 622

Only
IICO_CNTL[PT]
is cleared when a requested master transfer is complete; the remaining bits are
not affected.
Figure 22-8 illustrates the
IICO_CNTL.
HMT TCT CHT PT
I I I I
y y • •
101112 31 4 151 6 1 7 1
f f f
AMD RPST RW
Figure 22·8. IICO Control Register (IICO_CNTL)
0 HMT Halt Master Transfer If no transfer is in progress, no action is
o
Normal transfer operation.
taken.
1 Issue Stop signal on the IIC bus as soon
IICO_CNTL[PT] needs not be set.
as possible to halt master transfer.
If IICO_MDCNTL[EINT]
=
1, an interrupt is
generated.
1 AMD Addressing Mode Does not affect slave transfers.
a Use 7-bit addressing.
1 Use 1 a-bit addressing.
2:3
TCT Transfer Count
00 Transfer one byte.
01 Transfer two bytes.
10 Transfer three bytes.
11 Transfer four bytes.
4
RPST
Repeated Start
a Normal start operation
1 Use repeated Start function to start
transfer.
5 CHT Chain Transfer Completion of a requested transfer causes
a Transfer is only or last transfer.
a Stop signal to be issued on the IIC bus.
1 Transfer is one of a sequence of transfers
(but not last in sequence).
6
RW
Read/Write
o
Transfer is a write.
1 Transfer is a read.
7 PT Pending Transfer
a Most recent requested transfer is
complete.
1 Start transfer if bus is free.
Preliminary IIC Bus Interface 22·7