Overlapped Plb Transfers; Figure 2-1. Overlapped Plb Transfers - IBM PowerPC 405GP User Manual

transfer. Data acknowledge signals are required during the data acknowledge phase for each data
beat in a data cycle.
Note: For single-beat transfers, data acknowledge signals also indicate the end of the data transfer.
For line or burst transfers, the data acknowledge signals apply to each beat and indicate the
end of the data cycle only after the final beat.
2.1.5 Overlapped PLB Transfers
Figure 2-1 shows an example of overlapped PLB transactions on the read/write data buses with
pipelining. PLB address, read data, and write data buses are decoupled from one another, allowing
for address cycles to be overlapped with read or write data cycles, and for read data cycles to be
overlapped with write data cycles. The PLB split-bus transaction capability allows the address and
data buses to have different masters at the same time.
PLB address pipelining capability enables a new bus transfer to begin before an ongoing transfer
finishes. Address pipelining reduces overall bus latency on the PLB by enabling the latency
associated with a new transfer request to be overlapped with an ongoing data transfer in the same
direction.
PLB masters A and B each present a read request followed by a write request. Master B gets the bus
first, so its read is the primary read transaction. The master A address cycle begins as soon as the
master B address cycle ends. The master A read is taken as a secondary transfer. Writes follow
reads.
Cycle
PLB Clock
Master A
Master B
PLB Addr Bus
PLB Write Data
Bus
PLB Read Data
Bus
213 16 718 19 1101111121131141151161171181191201
'l1li Read
~IIIII
Write
~'
i
REO
i
REO
i
REO I)(fAA IREO
1
REO
1
REO I)(fAA
1
; i :
I ;
! . ,
.. Read
~'1111
I
wilte
~'
: : 1
~
l
Note:
XlAA
=
Xfer/AddrAck
XlDA
=
Xfer/DataAck
XlAA:A
=
XlAA Master A
XlAA:B
=
XlAA Master B
! . . . .
t ;
! '
i
Figure 2·1. Overlapped PLB Transfers
Note: A master can begin to request ownership of the PLB in parallel with the address cycle or data
cycle of another master bus transfer. Overlapped read and write data transfers and split-bus
transactions enable the PLB to operate at a very high bandwidth.
2-4 PPC405GP User's Manual
Preliminary