IBM PowerPC 405GP User Manual page 640

Embedded processor
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Chapter 23. GPIO Operations
This chapter describes the General Purpose I/O (GPIO) controller located on the on-chip peripheral
bus (OPS) of the PPC405GP. The GPIO controller allows flexible control of up to 23 multiplexed II0s
with user-defined functions.
23.1 GPIO Controller Overview
The GPIO Controller is an OPS macro that controls up to 23 bidirectional module
1/0
pins with user-
programmable functions. Each of these lOs are multiplexed with other signals to reduce the quantity
of module
1/0
on the PPC405GP package. Control for this multiplexing is performed using the
CPCO_CRO register. See "External Module Signals" on page 23-3 for more information.
The GPIO outputs can be programmed to emulate an open drain driver.
All module
1/0
inputs are synchronized to the OPSClk before being stored in the Input register.
All registers, except the Input Register, are both read and write accessible. The Input register is read-
only. Registers provide direct control of all GPIO Controller functions.
All register bits and core input and output signals maintain a bit-for-bit correspondence. For example,
GPI0_Out[20] is controlled by GPIOO_OR Register Sit 20.
23.2 Features
The GPIO Controller has the following features:
• Direct control of all functions from registers programmed via memory-mapped addresses
• Control of 23 bidirectional GPIO module pins
- Each GPIO output has programmable three-state control
- Each GPIO output is separately programmable to emulate an open drain driver
- Each GPIO input is observable from a register bit
Preliminary
GPIO Operations
23-1

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