PCI Command Register (PCICO_CMD) ............................................................................................. 17-31
PCI Status Register (PCICO_STATUS) .............................................................................................. 17-33
PCI Revision
10
Register (PCICO_REVID) ......................................................................................... 17-34
PCI Class Register (PCICO_CLS) ...................................................................................................... 17-35
PCI Cache Line Size Register (PCICO_CACHELS) ........................................................................... 17-35
PCI Built-In Self Test (BIST) Control Register (PCICO_BIST) ............................................................ 17-37
PCI PTM 1 BAR (PCICO_PTM1BAR) .................................................................................. : ............. 17-37
PCI PTM 2 BAR (PCICO_PTM2BAR) ................................................................................................ 17-38
PCI Subsystem Vendor
10
Register (PCICO_SBSYSVID) ................................................................. 17-39
PCI Subsystem
10
Register (PCICO_SBSYSID) ................................................................................ 17-39
PCI Capabilities Pointer (PCICO_CAP) .............................................................................................. 17-40
PCllnterrupt Line Register (PCICO_INTLN) ...................................................................................... 17-40
PCllnterrupt Pin Register (PCICO_INTPN) ........................................................................................ 17-41
PCI Minimum Grant Register (PCICO_MINGNT) ............................................................................... 17-41
PCI Maximum Latency Register (PCICO_MAXLTNCY) ..................................................................... 17-41
PLB Slave Error Syndrome Register
°
(PCICO_PLBBESRO) ............................................................ 17-45
Capability Identifier (PCICO_CAPID) .................................................................................................. 17-49
Next Item Pointer (PCICO_NEXTIPTR) .............................................................................................. 17-49
Error Handling ............................................................................................................................................. 17-55
PCI Master Abort .................................................................................................................................... 17-55
Power State Control ................................................................................................................................. 17-59
Changing Power States .......................................................................................................................... 17-60
PCI Bridge Reset and Initialization .............................................................................................................. 17-61
Address Map Initialization ....................................................................................................................... 17-61
Target Bridge Initialization ...................................................................................................................... 17-63
Type
°
Timing Diagrams ......................................................................................................................................... 17-64
PCI Timing Diagr9.m Descriptions .........................................................................................
~
................. 17-65
xlv
PPC405GP User's Manual
Preliminary