IBM PowerPC 405GP User Manual page 611

1/(56000) x (1
+
8
+
1
+
2) = 214.3Jls
So the timeout would occur after 857.1 Jls, if the above conditions hold.
When a timeout interrupt has occurred, it is cleared and the timer is reset when the processor reads
one character from the receiver FIFO.
When a timeout interrupt has not occurred, the timer is reset after a new serial character is received
or the processor reads the receiver FIFO.
21.4.1.2 Transmitter
Transmitter interrupts occur, as described below, when the transmitter FIFO and transmitter interrupts
are enabled by setting UARTx_FCR[FE]
=
1 and UARTx_IER[ETBEI]
=
1.
The transmitter holding register interrupt (UARTx_IIR = OxC2) occurs when transmit FIFO is empty,
and is cleared as soon as the transmitter holding register is written to or the IIR is read. One to 16
characters may be written to the transmitter FIFO while servicing this interrupt.
The transmitter FIFO empty indications are delayed by one character time minus the last stop bit time
whenever the following event occurs: UARTx_LSR[THRE]
=
1 and there were less than two bytes
simultaneously present in the transmit FIFO since the last UARTx_LSR[THRE]
=
1. If
UARTx_FCR[FE]
=
1 (FIFOs enabled), the first transmitter interrupt after changing UARTx_FCR[FE]
is immediate.
Receiver FIFO trigger level interrupts, received data available interrupts, and character timeouts all
have equivalent second interrupt priority. Current transmitter holding register empty interrupt and
Transmit FIFO empty have equivalent third interrupt priority.
21.4.2 Polled Mode
When UARTx_FCR[FE] = 1 (FIFOs enabled), and UARTx_IER[5:7] are all set to 0 (interrupts
disabled), the UART is in FIFO polled mode of operation. The receiver and transmitter are controlled
separately, so either can be in polled mode of operation. In polled mode, the user program must
check the UARTx_LSR to see the status of the receiver and/or transmitter.
UARTx_LSR3:6 specifies which errors (if any) have occurred. Character status errors are handled in
the same way as in interrupt mode. Since UARTx_IER[ELSI]
=
0, the IIR is not affected.
UARTx_LSR[DR] is set as long as there is at least one character in the receiver FIFO.
UARTx_LSR[THRE] indicates if the transmitter FIFO is empty. UARTx_LSR[TEMT] indicates if the
transmitter FIFO and the transmitter shift register are empty. UARTx_LSR[RFE] indicates if there are
any errors in the receiver FIFO.
In FIFO polled mode, there are no character timeout or trigger levels; however, the FIFOs are still
capable of holding characters.
21.5
UART
and Sleep Mode
Both UARTs can be placed in sleep mode via the UART sleep bits in the CPCO_ER register
(CPCO_ER[UARTO:UART1]). The most common usage would be to save a little power if one or both
of the UARTs were not going to be used.
21-16
PPC405GP User;s Manual Preliminary