Pci Bridge Block Diagram; Byte Ordering; Figure 17-1. Pci Bridge Block Diagram - IBM PowerPC 405GP User Manual

17.1.2 PCI Bridge Block Diagram
Figure 17-1 shows the PCI bridge block diagram.
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Processor Local Bus (PLB)
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1
Configu ration
!
PLB Slave Interface
~
Registers
PLB Master Interface
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~
Configure
~
~
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Read
Write
Buffer
Buffer
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,.
,
Interlock
Read
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Write
r
Buffer Buffer
PCI Master Interface
4
PCI Target Interface
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t
~
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Async
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PCI
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Arbiter
i i
...
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PCIBus
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Figure 17-1. PCI Bridge Block Diagram
17.1.3 Byte Ordering
The PCI bridge configuration register address space must be treated as little endian, as required by
PCI Specification, Version 2.2. In most cases data memory areas in PCI address space will be
configured and used in little end ian format. To provide for this, PCI configuration space and memory
map regions should be defined as little endian memory space by means of the corresponding entry in
the PPC405GP CPU's MMU or by means of the appropriate memory region bit in the Storage Little-
Endian Register (SLER) if the MMU is not being used. Because the endianness attribute in the SLER
can only be applied to 128 MB memory regions, this method of defining little end ian memory space for
PCI must be carefully considered in defining a system memory map.
Byte ordering and management of little endian memory space from a PowerPC CPU point of view is
described in detail in "Byte Ordering" on page 3-28. PowerPC architecture and CoreConnect bus
architecture both use a bit naming convention in which the most significant bit (msb) name
incorporates the numeral 0 and the least significant bit (Isb name for a 32-bit vector incorporates the
numeral 31. Table 17-1 shows the correspondence of address bit-naming conventions for PowerPC,
CoreConnect PLB, and PCI interface.
17-2
PPC405GP User's Manual
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