Prefetch Distance Down An Unresolved Branch Path; Prefetch Of Branches To The Ctr And Branches To The Lr; Preventing Inappropriate Speculative Accesses - IBM PowerPC 405GP User Manual

Two methods control speculative instruction fetching. If instruction address translation is enabled
(MSR[IR]
=
1), the G (guarded) field in the translation lookaside buffer (TLB) entries controls
speculative accesses.
If instruction address translation is disabled (MSR[IR]
=
0), the Storage Guarded Register (SGR)
controls speculative accesses for regions of memory. When a region is guarded (speculative fetching
is disallowed), instruction prefetching is disabled for that region. A fetch request must be completely
resolved (no longer speculative) before it is issued. There is a considerable performance penalty for
fetching from guarded storage, so guarding should be used only when required.
Note that, following any reset, the PPC405GP operates with all of storage guarded.
Note that when address translation is enabled, attempts to access guarded storage result in
instruction storage exceptions. Guarded memory is in most often needed with peripheral status
registers that are cleared automatically after being read, because an unintended access resulting
from a speculative fetch would cause the loss of status information. Because the MMU provides 64
pages with a wide range of page sizes as small as 1 KB, fetching instructions from guarded storage
should be unnecessary.
3.8.1.1 Prefetch Distance Down an Unresolved Branch Path
The fetcher will speculatively access up to five instructions down a predicted branch path, whether
taken or sequential. The unresolved branch is in the DCD stage of the instruction queue (see
"Instruction Processing" on page 3-33 for a description of the instruction pipeline). If PFBO and PFB1
are full, no further speculative accesses occur. If PFBO or PFB1 is empty, the fetcher requests the
next speculative instruction .trom the ICU; that instruction is placed in PFBO or PFB1. If the fetched
instruction is at the end of a cache line, and if PFB1 is empty, the fetcher requests the next cache line.
The instruction at the beginning of the cache line is placed in PFB1. In this case, five instructions are
speculatively accessed. The fetcher can speculatively access no more than four instructions (a cache
line) from the cache with a single request, assuming the speculative address is cachable.
If the address is non-cachable (as controlled by the I storage attribute), no more than two instructions
are speculatively accessed.
3.8.1.2 Prefetch of Branches to the eTR and Branches to the LR
When the instruction fetcher predicts that a bctr or blr instruction will be taken, the fetcher does not
attempt to fetch an instruction from the target address in the CTR or LR if an executing instruction
updates the register ahead of the branch. (See "Instruction Processing" on page 3-33 for a
description of the instruction pipeline). The fetcher recognizes that the CTR or LR contains data left
from an earlier use and that such data is probably not valid.
In such cases, the fetcher does not fetch the instruction at the target address until the instruction that
is updating the CTR or LR completes. Only then are the "correct" CTR or LR contents known. This
prevents the fetcher from speculatively accessing a completely "random" address. After the CTR or
LR contents are known to be correct, the fetcher accesses no more than five instructions down the
sequential or taken path of an unresolved branch, or at the address contained in the CTR or LR.
3.8.2 Preventing Inappropriate Speculative Accesses
A memory-mapped liD peripheral, such as a serial port having a status register that is automatically
reset when read provides a simple example of storage that should not be speculatively accessed. If
code is in memory at an address adjacent to the peripheral (for example, code goes from
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PPC405GP User's Manual Preliminary