Burst Read Transfer; Figure 16-12. External Master Arbitration, Single Read And Single Write - IBM PowerPC 405GP User Manual

To perform a single read operation the external master must:
• Place the desired address on PerAddrO:31.
• Indicate the requested data byte(s) on PerWBEO:3.
• Drive PerRiW high.
• Assert PerBLast to mark this as a single transfer.
• Request the transfer by driving and holding ExtReq low.
Cycle
PerClk
HoldPri
~~~~~
______
~--
____________
~c::J
HoldReq
--.....J
HoldAck
[L-J
'-----
I
ExtReq , \
i
~ 1/r--:-~i
'rL::J..,.. ... -' ,.- . . ..,...:
~~~---:----..,..---~-~~-----~_-~..,..I--~I ~--..,..~,',--~ !i!~~~--~
ExtAck
iLLD
IL-J
~
;
~
I '
~~--~~~-A~d~dre-s~so~~~ Addr~,.
ss 1 '
ct=::>-d
PerAddrO:31
=Pe----;rW-' - ' ; B=E=O--:3
~-----ihc:=::x
BE 0
c:::::::J.
i
BE 1
x::==:>--e:J
PerRiW
-~~--..jhc:=J
PerBLast
~
I\~----~-:-~~i~
!C7?'":\
i~
, !
PerDataO:31 " -____
---...J
Figure 16-12. External Master Arbitration, Single Read and Single Write
The EBM interface then converts this read request into a PLB transaction and reads the target
memory location. ExtAck then goes low when read data is available on PerData. Note that the
external master must not remove ExtReq until the cycle after ExtAck becomes active. In addition,
ExtReq must be high for at least one cycle between all external master transactions.
Write transfers are similar to reads except that the write data must be provided along with the address
and PerRIW is low to indicate a write. As with reads, ExtReq must be held until the cycle after ExtAck
is received.
16.5.4 Burst Read Transfer
Burst reads are preferred when accessing sequential addresses as they provide much better
performance. Figure 16-13 illustrates an external master burst read transaction. A burst read differs
from a single read in that PerBLast is held inactive for all but the last transfer of the burst. In addition,
the EBM only requires the address of the first burst element. Following each ExtAck the EBM uses
16-20 PPC405GP User's Manual