Pci Bridge Transaction Handling; Plb-To-Pci Transaction Handling; Pci Master Commands - IBM PowerPC 405GP User Manual

17.4 PCI Bridge Transaction Handling
The following sections discuss PCI bridge transactions and completion ordering.
17.4.1 PLB-to-PCI Transaction Handling
This section describes how the PCI bridge responds to read and write requests from a PLB master.
The PCI bridge decodes and accepts PLB transactions to different address ranges resulting in the
generation of memory, liD, configuration, interrupt acknowledge and special cycles on the PCI bus.
Table 17-5. Transaction Mapping: PLB
->
PCI
PLB Transaction
PCI Transaction
PLB Master
~
Bridge Bridge Mapping and Bridge (PCI Master Interface)
~
PCI
(PLB Slave Interface) Qualifications Target
Single-beat 1
~
a-byte Read 64KB or 56MB PCI I/O I/O Read
address range
Single-beat 1
~
a-byte Write
64KB or 56MB PCI I/O I/O Write
address range
Single-Beat 1
~
a-byte Read Access to PCICO_CFGDATA Configuration Read (Type 0, 1)
register
Single-Beat 1
~
a-byte Write Access to PCICO_CFGDATA Configuration Write (Type 0, 1)
register
Single-Beat 1
~
a-byte Read
PLB address decodes to Memory Read
PMMO, PMM1, or PMM2,
nonprefetchable
Burst Read PLB address decodes to Memory Read
PMMO, PMM1, or PMM2,
nonprefetchable
PLB 4-word and a-word Line Reads PLB address decodes to Memory Read Line
PMMO, PMM1, or PMM2
Single-Beat 1
~
4-byte Read
PLB address decodes to Memory Read Multiple
PMMO, PMM1, or PMM2,
nonprefetchable
Burst Read PLB address decodes to Memory Read Multiple
PMMO, PMM1, or PMM2,
nonprefetchable
Single-Beat 1
~
4-byte Write PLB address decodes to Memory Write
PMMO, PMM1, or PMM2
Burst Write PLB address decodes to Memory Write
PMMO, PMM1, or PMM2
Single-Beat 1
~
4-byte Read Address OxFEDOOOOO Interrupt Acknowledge
Single-Beat 1
~
4-byte Write Address OxFEDOOOOO Special Cycle
-
Not supported Memory Write and Invalidate
-
Not supported Memory Write Line
17.4.1.1 PCI Master Commands
The type of cycle generated to the PCI bus depends on the PLB address, the type of PLB transfer,
and the data size. The following sections describe the transaction types supported and outlines the
translation of commands from one bus to the other.
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PPC405GP User's Manual Preliminary