Input Reference Clock (Sysclk) - IBM PowerPC 405GP User Manual

Several strapping values are required to correctly configure the PPC405GP. When setting the values,
pay close attention to the following information to avoid accidentally configuring the controller in an
unusable state.
For any acceptable SysClk input, the VCO frequency is set by the feedback and forward dividers, and
the CPU to PLB divider, as shown in the following equation:
VCO = Reference Clock x
M
where
M
=
Feedback Divide x Forward Divide x CPU to PLB Divide
For example, with an input reference frequency of 33.33 MHz, feedback divider of 3, CPU to PLB
divider of 2, and forward divider of 3, the VCO frequency at which the PLL stabilizes is 600 MHz.
Strap selection for PLL tuning depends upon the value of M, which can range from 6 to 32. The upper
limit is based on a minimum input reference clock frequency of 25 MHz and a maximum VCO
frequency of 800 MHz. The lower limit is based on a maximum input reference clock of 66 MHz and a
minimum VCO frequency of 400MHz. M decreases as the reference clock frequency increases.
7.2 Input Reference Clock (SysClk)
The input reference clock, SysClk, must be between 25 MHz and 66 MHz for the PLL to achieve a
stable lock. Input clocks outside this range are not supported. When synchronous PCI mode is
selected, clock generation logic ensures that the internally generated PCI clock and SysClk are
phase-aligned. This means that rising edges will coincide as long as the frequencies are the same. In
most cases, the input reference clock is expected to be the same as the PCI clock provided to other
PCI devices outside of the 405GP. Therefore, the phase alignment that automatically occurs ensures
that the internally generated PCI clock matches the clock used by other PCI devices.
Clock generation logic also ensures that the internally generated peripheral clock (PerClk) is phase-
aligned with SysClk, as long as both run at the same clock frequency. This is useful when an external
device, such as an external master, cannot be synchronized with the PPC405GP PerClk.
7-2 PPC405GP User's Manual Preliminary