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occurs for the pending condition or COIHlilions
having the highest priority.
The priorities for external-interruption requests
in descending order are as follows:
Interval timer, interrupt key, external signals 2-7
Clock comparator
CPU timer
The interval timer, interrupt key, and external
signals 2-7 are of equal priority; if more than one
of these conditions is pending and allowed, the
conditions are indicated concurrently. J\.ll other
requests are honored one at a time.
Clock Comparator
An interruption request for the clock comparator
exists whenever either of the following conditions is
met:
1. The time-of-day clock is in the set or not-set
state, and the value of the clock comparator is
less than the value in the compared portion of
the time-of-day clock, both compare values
being considered unsigned binary integers.
2. The time-of-day clock is in the error or
not-operational state.
If
the condition responsible for the request is
removed before the request is honored, the request
does not remain pending, and no interruption
occurs. Conversely, the request is not cleared by
the interruption, and, if the condition persists, more
than one interruption may result from a single
occurrence of the condition.
The clock-comparator condition is indicated by
an external-interruption code of 1004 (hex).
The subclass-mask bit is in bit position 20 of
control register O. This bit is initialized to zero.
CPU Timer
An interruption request for the CPU timer exists
whenever the CPU-timer value is negative (bit 0 of
the CPU timer is one). If the value is made
positive before the request is honored, the request
does not remain pending, and no interruption
occurs. Conversely, the request is not cleared by
the interruption, and, if the condition persists, more
than one interruption may occur from a single
occurrence of the condition.
The CPU-timer condition is indicated by an
external-interruption code of 1005 (hex).
The subclass-mask bit is in bit position 21 of
control register O. This bit is initialized to zero.
External Signal
An interruption request for an external signal is
generated when a signal is received on one or more
6-8
IBM 4300 Processors Principles of Operation
of the signal-in lines. Up to six signal-in lines may
be connected, providing for external signal 2
through external signal 7. The request is preserved
and remains pending in the CPU until it is cleared.
The pending request is cleared when it causes an
interruption and by program reset.
Facilities are provided for holding a separate
external-signal request pending for each of the six
lines.
External signals 2-7 are indicated by setting to
one interruption -code bits 10-15, respectively. Bits
0-7
are set to zeros, and any other bits in the
rightmost byte are set to zeros unless set to ones
for other conditions that are concurrently indicated.
All external signals are subject to control by the
subclass-mask bit in bit position 26 of control
register O. This bit is initialized to one.
External signaling is independent of I/O
operations and interruptions.
Programming Note
The pattern presented in bit positions 10-15 of the
interruption code depends on the pattern received
before the interruption is taken. Because of circuit
skew, all simultaneously generated external signals
do not necessarily arrive at the same time, and
some may not be included in the external
interruption resulting from the earliest signals.
These late signals may cause another interruption
to be taken.
Interrupt Key
An interruption request for the interrupt key is
generated when the operator activates that key.
The request is preserved and remains pending in
the CPU until it is cleared. The pending request is
cleared when it causes an interruption and by
program reset.
When the interrupt key is activated while the
CPU is in the load state, it depends on the model
whether an interruption request is generated or the
condition is lost.
The interrupt-key condition is indicated by
setting bit 9 in the interruption code to one and by
setting bits 0-7 to zeros. Bits 8 and. 10-15 are
zeros unless set to ones for other conditions that
are concurrently indicated.
The subclass-mask bit is in bit position 25 of
control register O. This bit is initialized to one.
Interval Timer
An interruption request for the interval timer is
generated when the value of the interval timer is
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